Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

Abstract: A composite conducive to heat dissipation of an LED-mounted substrate includes a ceramic layer being of a thermal conductivity of 20˜24 W/mK; a metal layer being of a thermal conductivity of 100˜200 W/mK; and a graphite layer being of an in-plane thermal conductivity of 950 W/mK and a through-plane thermal conductivity of 3 W/mK, wherein the metal layer is disposed between the ceramic layer and the graphite layer. The composite has one side displaying satisfactory insulation characteristics and the other side displaying satisfactory heat transfer characteristics. The composite incurs low material costs and requires a simple manufacturing process.

Abstract: A multi-cluster, multi-processor computing system performs a cache flushing method. The method begins with a cache maintenance hardware engine receiving a request from a processor to flush cache contents to a memory. In response, the cache maintenance hardware engine generates commands to flush the cache contents to thereby remove workload of generating the commands from the processors. The commands are issued to the clusters, with each command specifying a physical address that identifies a cache line to be flushed.

Abstract: A method for removing boron from boron-containing waste water includes performing oxidation/coagulation treatment on the boron-containing waste water in the presence of an oxidant (such as hydrogen peroxide) and a coagulant (such as barium hydroxide) to greatly reduce the boron content of the boron-containing waste water and then removing residual boron therefrom by an ion-exchange resin or reverse osmosis, such that the waste water thus treated meets effluent standards.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: The protection circuit for a power source of an electronic device capable of providing a certain range of current values to a peripheral unit comprising a power storage unit. The protection circuit comprises a first and second charging paths and a voltage detector. The voltage detector switches the first charging path to turn on the first switch, when the voltage value of the power storage unit 30 is lower than the threshold voltage, the power source can charge the power storage unit by the first switch, wherein the current limiting device limits the current value of first charging path to lower than a predetermined. The voltage detector switches the first charging path to breakup the second switch and the voltage detector switches to the first charging path to turn on the first switch.

Abstract: A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the standard cells. Typically these standard cells are arranged in a row between two power buses. In this invention the standard cells are partitioned into first cells and second cells which can be combined to form the standard cell circuit. The first cells are arranged in a first row and the second cells are arranged in a second row. A first power bus is located above the first row of first cells and a second power bus is located below the second row of second cells. The first power bus and second power bus are electrically connected together. The first power bus supplies a first power supply voltage to the first cells and the second power bus supplies the first power supply voltage to the second cells.

Abstract: The protection circuit for a power source of an electronic device capable of providing a certain range of current values to a peripheral unit comprising a power storage unit. The protection circuit comprises a first and second charging paths and a voltage detector. The voltage detector switches the first charging path to turn on the first switch, when the voltage value of the power storage unit 30 is lower than the threshold voltage, the power source can charge the power storage unit by the first switch, wherein the current limiting device limits the current value of first charging path to lower than a predetermined. The voltage detector switches the first charging path to breakup the second switch and the voltage detector switches to the first charging path to turn on the first switch.

Abstract: A electronic peripheral device. The electronic peripheral device is coupled to an electronic system and selectively coupled to either of a first wireless network or a second wireless network. The electronic peripheral device comprises a first module for accessing the first wireless network, a second module for accessing the second wireless network, and a processor. When the electronic system is coupled to the first wireless network, signals from the first wireless network are received by the first module and transmitted to the electronic system through the second module, and signals from the electronic system transmitted to the first wireless network are controlled by the processor. When the electronic system is coupled to the second wireless network, signals from the second wireless network are received by the second module and transmitted to the electronic system, and signals from the electronic system transmitted to the second wireless network are controlled by the processor.

Abstract: A layout structure and method are described for the layout of chips having libraries of standard cells which minimizes voltage fluctuations on power buses caused by switching circuits in the standard cells. Typically these standard cells are arranged in a row between two power buses. In this invention the standard cells are partitioned into first cells and second cells which can be combined to form the standard cell circuit. The first cells are arranged in a first row and the second cells are arranged in a second row. A first power bus is located above the first row of first cells and a second power bus is located below the second row of second cells. The first power bus and second power bus are electrically connected together. The first power bus supplies a first power supply voltage to the first cells and the second power bus supplies the first power supply voltage to the second cells.

Abstract: Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

Abstract: Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

Abstract: A conductive interconnection for an integrate circuit between a protected node and a protecting node and its method are disclosed. The conductive interconnection comprises a stacking connector, a routing connector and a top conductive line. The stacking connector is formed to connect the protected node, which is constructed by at least one inner conductive line and at least one conductive plug, alternately. The inner conductive line has a length lower than a threshold value constrained by antenna effect. Moreover, the routing connector, extending toward the stacking connector, is formed to connect the protecting node. The top conductive line is used to connect the stacking connector and the routing connector. Accordingly, the protected node is disconnected from the protecting node prior to the formation of the top conductive line.