Abstract: The present disclosure provides an excitation fuse with a conductor and a fusant being sequentially broken, the excitation fuse comprising a housing and a cavity in the housing, wherein at least one conductor is provided to be inserted in the housing and the cavity and has two ends connected with an external circuit; at least one fusant is provided in parallel on the conductor; an excitation device and a breaking device are mounted in the cavity at one side of the conductor; the excitation device may receive an external excitation signal to act to drive the breaking device to sequentially form at least one fracture on the conductor and the fusant respectively; and at least one fracture on the conductor is connected in parallel with the fusant.

Abstract: Methods and systems for image generation include generating a latent representation of an image, modifying the latent representation of the image based on a trained attribute classifier and a specified attribute input, and decoding the modified latent representation to generate an output image that matches the specified attribute input.

Abstract: An accelerator circuit including a control interface to receive a stream of instructions, a first memory to store an input data, and an engine circuit including a dispatch circuit to decode an instruction of the stream of instructions into a plurality of commands, a plurality of queue circuits, each of the plurality of queue circuits supporting a queue data structure to store a respective one of the plurality of commands decoded from the instruction, and a plurality of command execution circuits, each of the plurality of command execution circuits to receive and execute a command extracted from a corresponding one of the plurality of queues.

Abstract: A system includes a memory to store an input data, an accelerator circuit comprising an input command execution circuit, a neuron matrix command execution circuit, and an output command execution circuit, and a processor, communicatively coupled to the memory and the accelerator circuit, to generate a stream of instructions from a source code targeted the accelerator circuit, each one of the stream of instructions comprising at least one of an input command, a neuron matrix command, or an output command, and issue the stream of instructions to the accelerator circuit for execution by the input command execution circuit, the neuron matrix command execution circuit, and the output command execution circuit.