Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

Abstract: The disclosed device includes a first node, a second node, a link, and flow-control circuitry configured to transmit data through the link, from the first node to the second node, at a designated frequency corresponding to the lowest of three maximum frequencies (e.g., a first maximum frequency at which the first node is predicted to be able to release data, a second maximum frequency at which data is predicted to be able to pass through the link from the first node to the second node, and a third maximum frequency at which the second node is predicted to be able to receive data). Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An exemplary method for performing lane-specific error detection in high-speed data links involves receiving, at a receiver, an ordered set of data from a transmitter communicatively coupled to the receiver via a data link. The exemplary method also involves identifying, in the ordered set of data, an error-detection reference. The exemplary method further involves performing, in connection with one data lane of the data link, an error-detection operation on the ordered set of data based at least in part on the error-detection reference. Various other devices, systems, and methods are also disclosed.

Abstract: An exemplary method for performing lane-specific error detection in high-speed data links involves receiving, at a receiver, an ordered set of data from a transmitter communicatively coupled to the receiver via a data link. The exemplary method also involves identifying, in the ordered set of data, an error-detection reference. The exemplary method further involves performing, in connection with one data lane of the data link, an error-detection operation on the ordered set of data based at least in part on the error-detection reference. Various other devices, systems, and methods are also disclosed.

Abstract: An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

Abstract: The present invention relates to a kind of microwave cavity for atomic frequency standard, which consists of slotted tube, cylindrical cavity body, dielectric ring, heating filament, screw bolt for adjustment of cavity frequency. Its characteristics are listed as follows: 1. There are slots and electrodes at the upside of slotted tube. 2. The slotted tube and the bottom cap of the cavity are made as a whole. 3. The Rb absorption cell is inserted in the slotted tube. 4. The dielectric ring is inserted between the slotted tube and the cylindrical cavity body. 5. There is one or more screw hole in the wall of cylindrical cavity body. 6. One or more screw bolt for adjustment of cavity frequency is installed into the screw hole.