Abstract: An automatic layout method for a pad ring used for optimizing the electrostatic discharging capacity of a chip, comprising: determining, on the basis of information of a selected process library and of package constraint information, the types and number of signal lead modules of a chip, and combined with designed total power consumption data, determining the types of power supply lead modules and a basic required number corresponding to each type of power supply lead modules; producing, on the basis of the types and the numbers of the signal lead modules and of that of the power supply lead modules and of the package constraint information, groups of lead modules to be laid out respectively for four boundaries; executing a first automatic layout with respect to each boundary, when a first boundary module is inserted, sequentially polling and calling a second subprogram and a third subprogram, respectively used for inserting the signal lead modules, a first power supply lead modules and/or a second power supp