Abstract: The invention provided an ion implantation system. The ion implantation system comprises an ion emitting device and a target plate device; the target plate device comprises a graphite electrode unit and a power supply unit; the graphite electrode unit is mounted on the lower end of a support frame, and the graphite electrode unit is a hollow structure; the graphite electrode unit comprises a graphite electrode and a hollow region I, the graphite electrode is connected to the power supply unit; the area of the hollow region I is smaller than that of the wafer to be processed, and the sum of the area of the graphite electrode and the area of the hollow region I is larger than an implantation area of the ion beam.

Abstract: The invention provided an ion implantation system. The ion implantation system comprises an ion emitting device and a target plate device; the target plate device comprises a graphite electrode unit and a power supply unit; the graphite electrode unit is mounted on the lower end of a support frame, and the graphite electrode unit is a hollow structure; the graphite electrode unit comprises a graphite electrode and a hollow region I, the graphite electrode is connected to the power supply unit; the area of the hollow region I is smaller than that of the wafer to be processed, and the sum of the area of the graphite electrode and the area of the hollow region I is larger than an implantation area of the ion beam.

Abstract: A method of fabricating PMOS devices with embedded SiGe is disclosed. Prior to the selective epitaxial growth of SiGe, Ge element is implanted to the source/drain recesses and an annealing process is performed to form a strained SiGe alloy layer. Then, the strained SiGe alloy layer is used as a base layer on which another strained SiGe alloy layer is grown continually by an selective epitaxy process, so as to avoid a direct contact between the epitaxially grown strained SiGe alloy layer and the silicon substrate and reduce the defects formed at the SiGe/Si interfaces. Therefore, the stress can be applied to the PMOS channel regions without causing junction current leakage due to the defects at the SiGe/Si interfaces, which enhances the electrical performance of the PMOS devices. The fabrication method is also compatible with the conventional CMOS process.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

Abstract: A method for repairing damages to sidewalls of an ultra-low dielectric constant film is disclosed by the present invention comprises the following steps: depositing an ultra-low dielectric constant film on an semiconductor substrate; dry-etching the ultra-low dielectric constant film to form a sidewall structure thereof; performing wet cleaning by using a chemical agent containing an unsaturated hydrocarbon having —O—C(Re)x; and performing ultraviolet curing. The present invention can restore pores size and porosity of the ultra-low dielectric constant film, and to keep effective dielectric constant to a minimum.

Abstract: A method for repairing damages to sidewalls of an ultra-low dielectric constant film is disclosed by the present invention comprises the following steps: depositing an ultra-low dielectric constant film on an semiconductor substrate; dry-etching the ultra-low dielectric constant film to form a sidewall structure thereof; performing wet cleaning by using a chemical agent containing an unsaturated hydrocarbon having —O—C(Re)x; and performing ultraviolet curing. The present invention can restore pores size and porosity of the ultra-low dielectric constant film, and to keep effective dielectric constant to a minimum.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.