Abstract: A finite field inverter is disclosed, wherein the finite field inverter includes an input port, an output port and a search tree inverse circuit configured to perform an inverse operation of the operand a(x) in the finite field GF(2n) based on a search tree structure. The search tree inverse circuit is provided with a left search tree and a right search tree. The left search tree and the right search tree each includes tree nodes for processing inverse operations over the finite field GF(2n) and connecting wires connected between the tree nodes. The tree nodes include a root node, internal nodes and leaf nodes. Each path from the root node to a leaf node represents an element in the finite field GF(2n). The connecting wires between the tree nodes connect the path representing the operand a(x) with the path representing the inversion result b(x) .

Abstract: The present invention relates to a parallel device for solving linear equations over finite fields, including a processor, an input port, an output port, a pivot finding component, a partial inversion component, a normalization component and an elimination component. The processor is connected to each of the pivot finding component, the partial inversion component, the normalization component, the elimination component, and the input port and the output port. The partial inversion component is connected to the elimination component and the normalization component. The pivot finding component is connected to the elimination component. The present invention enables parallel computing to a certain extent with fast solving speed and simple design, and thus can be widely used in various engineering fields.

Abstract: A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).

Abstract: A finite field inverter is disclosed, wherein the finite field inverter includes an input port, an output port and a search tree inverse circuit configured to perform an inverse operation of the operand ?(x) in the finite field GF (2n) based on a search tree structure. The search tree inverse circuit is provided with a left search tree and a right search tree. The left search tree and the right search tree each includes tree nodes for processing inverse operations over the finite field GF (2n) and connecting wires connected between the tree nodes. The tree nodes include a root node, internal nodes and leaf nodes. Each path from the root node to a leaf node represents an element in the finite field GF (2n). The connecting wires between the tree nodes connect the path representing the operand ?(x) with the path representing the inversion result b(x) .

Abstract: The present invention relates to a parallel device for solving linear equations over finite fields, including a processor, an input port, an output port, a pivot finding component, a partial inversion component, a normalization component and an elimination component. The processor is connected to each of the pivot finding component, the partial inversion component, the normalization component, the elimination component, and the input port and the output port. The partial inversion component is connected to the elimination component and the normalization component. The pivot finding component is connected to the elimination component. The present invention enables parallel computing to a certain extent with fast solving speed and simple design, and thus can be widely used in various engineering fields.

Abstract: A group key management approach based on linear geometry is disclosed.

Abstract: A constant temperature outlet structure is disclosed. A wall is disposed inside a housing of the constant temperature outlet structure. A cavity and an outlet pipeline are separated by the wall. A hose joint is disposed on the wall. A first hole of the housing is disposed corresponding to the outlet pipeline and a second hole is disposed at the wall. Two ends of the second hole are respectively connecting the cavity and the first hole. Thereby, the electroplating solution accumulated in the cavity surrounding the hose joint can be flowed downwardly from the second hole, through the first hole, and then discharged when the constant temperature outlet structure is slantwise hanged.

Abstract: A hierarchical group key management approach based on linear geometry is disclosed.

Abstract: A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).

Abstract: A constant temperature outlet structure is disclosed. A wall is disposed inside a housing of the constant temperature outlet structure. A cavity and an outlet pipeline are separated by the wall. A hose joint is disposed on the wall. A first hole of the housing is disposed corresponding to the outlet pipeline and a second hole is disposed at the wall. Two ends of the second hole are respectively connecting the cavity and the first hole. Thereby, the electroplating solution accumulated in the cavity surrounding the hose joint can be flowed downwardly from the second hole, through the first hole, and then discharged when the constant temperature outlet structure is slantwise hanged.

Abstract: A hierarchical group key management approach based on linear geometry is disclosed.

Abstract: A group key management approach based on linear geometry is disclosed.

Abstract: This invention publishes a secure group key management approach based upon N-dimensional hypersphere. After initialization, the GC admits the new members and assigns identifiers to them when there are new members joining the group, and deletes the leaving members' private information when there are members leaving the group. If a lot of members join and other members leave the group at the same time, the GC deletes the leaving members' private information, admits the new members, assigns indemnifiers to the new members, and then chooses mapping parameters, mapping each member's and its private information to the points in a multi-dimensional space. The GC calculates the central point of the hypersphere, and publishes the central point, the mapping parameter and the identifiers of leaving members if there are members leave. The group members calculate the mapping points, and then calculate the group keys.

Abstract: In a redundant wireless base station, a first baseband processing unit is coupled to a first radio unit and a second baseband processing unit is coupled to a second radio unit. A link couples the first baseband processing unit and the second baseband processing unit. The link allows at least one of the first baseband processing unit and the second baseband processing unit to one or more of transmit and receive via the first radio unit and the second radio unit. A buffer is associated with the link. The buffer is configured to synchronize one or more of transmission and reception via the first radio unit and the second radio unit.

Abstract: A redundant base station including a first baseband processing unit and at least a second baseband processing unit. The first baseband processing unit and the at least a second baseband processing unit are coupled by a link. The link is configured to communicate activity status information, operational status information, and reset control signals between the first baseband processing unit and the at least a second baseband processing unit.

Abstract: In a redundant wireless base station, a redundancy parameter solicitation is sent by a first baseband processing unit via a multicast to a local area network including at least a second baseband processing unit. Advertised redundancy parameters are received via a multicast to the local area network from the second baseband processing unit.

Abstract: In a redundant wireless network, a first baseband processing unit is defined as an active baseband processing unit and a second baseband processing unit as a standby baseband processing unit. An active address is associated with the first baseband processing unit and a standby address is associated with the second baseband processing unit. Subscriber traffic is routed to the first baseband processing unit via the active address. If the second baseband processing unit becomes an active baseband processing unit and the first baseband processing unit becomes a standby baseband processing unit, he active address is associated with the second baseband processing unit, and the standby address is associated with the first baseband processing unit. Subscriber traffic is routed to the second baseband processing unit via the active address.