Patents by Inventor Shao-Hui Wu
Shao-Hui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250105057Abstract: An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.Type: ApplicationFiled: September 22, 2023Publication date: March 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Kuan Lee, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chieh-Han Wu, Yu-Hao Yeh
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Patent number: 11011649Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.Type: GrantFiled: July 5, 2018Date of Patent: May 18, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
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Patent number: 10644166Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.Type: GrantFiled: September 13, 2018Date of Patent: May 5, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
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Patent number: 10629748Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.Type: GrantFiled: July 20, 2017Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pengfei Guo, Shao-Hui Wu, Hai Biao Yao, Yu-Cheng Tung, Yuanli Ding, Zhibiao Zhou
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Patent number: 10475932Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.Type: GrantFiled: November 30, 2017Date of Patent: November 12, 2019Assignee: Untied Microelectronics Corp.Inventors: Shao-Hui Wu, Yu-Cheng Tung
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Patent number: 10403743Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.Type: GrantFiled: July 20, 2017Date of Patent: September 3, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Xiang Li, Shao-Hui Wu, Hsiao Yu Chia, Yu-Cheng Tung
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Publication number: 20190131456Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.Type: ApplicationFiled: November 30, 2017Publication date: May 2, 2019Applicant: United Microelectronics Corp.Inventors: Shao-Hui Wu, Yu-Cheng Tung
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Publication number: 20190109199Abstract: An oxide semiconductor device includes an oxide semiconductor channel layer, a first gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide semiconductor channel layer includes a channel region. The first gate dielectric layer is disposed on the oxide semiconductor channel layer. The first gate electrode is disposed on the first gate dielectric layer. The source electrode and the drain electrode are disposed at two opposite sides of the first gate electrode in a first direction respectively. The first gate electrode includes a metal material with a work function higher than 4.7 electron volts (eV). A thickness of the oxide semiconductor channel layer is smaller than one third of a length of the channel region in the first direction.Type: ApplicationFiled: October 5, 2017Publication date: April 11, 2019Inventors: HAI BIAO YAO, Shao-Hui Wu, Xiang Li, HSIAO YU CHIA, Yu-Cheng Tung
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Publication number: 20190081183Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor channel layer, a second oxide semiconductor channel layer, a gate dielectric layer, and a gate electrode. The first patterned oxide semiconductor channel layer is disposed on the substrate. The second patterned oxide semiconductor channel layer is disposed on the first patterned oxide semiconductor channel layer and covers a side edge of the first patterned oxide semiconductor channel layer. The gate dielectric layer is disposed on the second patterned oxide semiconductor channel layer. A top surface of the second patterned oxide semiconductor channel layer is fully covered by the gate dielectric layer. The gate electrode is disposed on the gate dielectric layer. A projection area of the gate electrode in a thickness direction of the substrate is smaller than a projection area of the second patterned oxide semiconductor channel layer in the thickness direction.Type: ApplicationFiled: October 15, 2017Publication date: March 14, 2019Inventors: Xiang Li, Shao-Hui Wu, HSIAO YU CHIA, Yu-Cheng Tung
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Publication number: 20190027589Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.Type: ApplicationFiled: July 20, 2017Publication date: January 24, 2019Inventors: Xiang Li, Shao-Hui Wu, HSIAO YU CHIA, Yu-Cheng Tung
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Publication number: 20190027607Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.Type: ApplicationFiled: September 13, 2018Publication date: January 24, 2019Inventors: ZHIBIAO ZHOU, Shao-Hui Wu, Chi-Fa Ku
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Publication number: 20180358475Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.Type: ApplicationFiled: July 20, 2017Publication date: December 13, 2018Inventors: PENGFEI GUO, Shao-Hui Wu, HAI BIAO YAO, Yu-Cheng Tung, Yuanli Ding, ZHIBIAO ZHOU
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Patent number: 10147614Abstract: A method of manufacturing an oxide semiconductor transistor is provided in the present invention, which includes the step of providing an oxide semiconductor transistor on the front side of a substrate, attaching a wafer on the front side of the substrate, forming a contact hole extending from the back side of the substrate to the oxide semiconductor layer of the oxide semiconductor transistor, and filling the contact hole with metal material to form a back gate of the oxide semiconductor transistor.Type: GrantFiled: January 8, 2018Date of Patent: December 4, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Xiang Li, Shao-Hui Wu, Hsiao Yu Chia, Yu-Cheng Tung
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Publication number: 20180331233Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.Type: ApplicationFiled: July 5, 2018Publication date: November 15, 2018Inventors: ZHIBIAO ZHOU, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
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Patent number: 10115786Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.Type: GrantFiled: November 15, 2016Date of Patent: October 30, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin
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Patent number: 10102907Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.Type: GrantFiled: December 19, 2016Date of Patent: October 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Chen-Bin Lin, Chi-Fa Ku, Shao-Hui Wu
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Patent number: 10103273Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.Type: GrantFiled: March 1, 2017Date of Patent: October 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
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Patent number: 10102475Abstract: A control circuit including a first switch to a third switch, an inverter, a first capacitor and a second capacitor. The first switch includes a first terminal receiving a weighting signal, and a second terminal. The second switch includes a first terminal, a control terminal coupled to the second terminal of the first switch, and a second terminal coupled to a reference voltage terminal. The third switch includes a first terminal coupled to the reference voltage terminal, a control terminal, and a second terminal. The inverter includes an input terminal coupled to a data input terminal, and an output terminal. The first capacitor is coupled between the data input terminal and the control terminal of the second switch. The second capacitor is coupled between the output terminal of the inverter and the control terminal of the third switch.Type: GrantFiled: November 1, 2017Date of Patent: October 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yun-Yuan Wang, Shao-Hui Wu
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Patent number: 10043917Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.Type: GrantFiled: March 3, 2016Date of Patent: August 7, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
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Patent number: 9966428Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.Type: GrantFiled: January 15, 2016Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin