Patents by Inventor Shaojian Hu

Shaojian Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471739
    Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 18, 2016
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Zheng Ren, Shaojian Hu, Wei Zhou, Shoumian Chen, Yuhang Zhao
  • Patent number: 9466699
    Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: October 11, 2016
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Ao Guo, Zheng Ren, Shaojian Hu, Wei Zhou
  • Publication number: 20160268396
    Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.
    Type: Application
    Filed: July 18, 2014
    Publication date: September 15, 2016
    Inventors: Ao Guo, Zheng Ren, Shaojian Hu, Wei Zhou
  • Publication number: 20140351779
    Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.
    Type: Application
    Filed: November 20, 2012
    Publication date: November 27, 2014
    Inventors: Zheng Ren, Shaojian Hu, Wei Zhou, Shoumian Chen, Yuhang Zhao