Abstract: An embodiment of the present disclosure relates to a method of controlling a power amplifier (PA). The PA can comprise a main PA path and an auxiliary PA path. The auxiliary PA path can have a plurality of turn-on settings. The method can comprise: determining a power back off gain and a lower bound gain for the PA; and performing an iterative auxiliary PA turn-on setting selection process. The selection process can comprise: determining an instantaneous power input to the PA; based on the instantaneous power input, choosing a turn-on setting in the plurality of turn-on settings of the auxiliary PA path that causes an instantaneous gain of the PA to be between the power back off gain and the lower bound gain; and applying the chosen turn-on setting to the auxiliary PA path.

Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

Abstract: Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.

Abstract: A decorative switch assembly for outlet boxes wherein the switch actuator and the face plate are metallic and screwless. The assembly is grounded by using U-shaped sheet metals.

Abstract: “Confirmed with USPTO that no abstract was provided.

Abstract: A thin switch plate assembly for covering and mounting switches includes of a face plate attached to a base plate by a snap-fit connection to provide a screwless appearance.

Abstract: A novel cover plate assembly includes of two decorative face plates and a base plate for mounting electrical devices. The two face plates fabricated from steel plate are screwless and provide noble decorative appearances after the surfaces properly treated. The inner face plate is snapped into the base plate through a snap fit connection. The outer face plate is attached to inner face plate through a snap fit connection. The base plate can be molded of any flame retardant materials.

Abstract: A novel cover plate assembly comprising of two decorative face plates and a base plate for mounting electrical devices. The two face plates fabricated from steel plate are screwless and provide noble decorative appearances after the surfaces properly treated. The inner face plate is snapped into the base plate through a snap fit connection. The outer face plate is attached to inner face plate through a snap fit connection. The base plate can be molded of any flame retardant materials.

Abstract: A novel cover plate assembly comprising of a face plate and a base plate for mounting a switch mechanism having a yoke plate with the spacing of screw holes at the yoke plate the same as that of a wall box and that of said base plate provides a universal switch mounting system for any devices of any types. The decorative face plate is free of mounting screw holes and is snapped into the base plate through a snap fit connection. The cover plate assembly made of metal is suitable for high-class wall decorations.

Abstract: A thin switch plate assembly for covering and mounting switches comprised of a face plate attached to a base plate by a snap-fit connection to provide a screwless appearance.