Abstract: The present disclosure discloses a method for manufacturing a NOR flash. The drain area groove and the peripheral isolation grooves are first formed and filled with the trench isolation oxide, followed by the formation of the source area groove, and then the SiH4 layer is deposited. Due to the poor filling property of SiH4, the air gap may be formed at the source area groove with a small gap, and at this time, the drain area groove in the drain area of the storage area and the peripheral isolation groove in the logic area both have been filled and thus are unaffected. The method for manufacturing a NOR flash of the present disclosure allows the formation of the source air gap of the NOR flash based on a post-source preparation process and good filling of the drain, reducing the coupling effect between the source polysilicon gates.

Abstract: The present disclosure provides a method of reducing damage to floating gate polysilicon during etching. The method includes: forming a floating gate thicker than 400 ? on a tunneling oxide layer, forming a first region including a portion of the floating gate from the bottom to the 400 ? thickness, and forming a second region including a portion of the floating gate above the 400 ? thickness; performing carbon-doping deposition into the first region of the floating gate, wherein a carbon doping process is arranged to be in gradually decreasing flow rate in a direction from the bottom of the floating gate up to the 400 ? thickness, and the second region is not subjected to carbon doping; forming a stack layer including silicon oxide, silicon nitride, and silicon oxide on the floating gate; and forming a control gate on the stack layer.

Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.

Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.