Abstract: Mechano-chemical wastewater treatment equipment to treat wastewater containing heavy metals to form drainage. An intermediate sewage tank has a sewage inlet and a sewage outlet, and stores wastewater to be treated and sewage formed during the treatment process. At least one mechano-chemical reactor conducts the mechano-chemical reaction between the wastewater and zero-valent iron nanoparticles through a ball milling treatment. A separator to separate a slurry produced by the reactor into solids and liquids. The separator has a slurry inlet, a liquid outlet, and a sludge outlet. The reactor is a ball milling device having a reactor shell with a reaction chamber internally formed, a feeding inlet for the slurry to enter the reaction chamber and a discharge outlet for the slurry to flow out of the reaction chamber. A rotor is set inside the reaction chamber and a driving mechanism rotates the rotor.

Abstract: A DC/AC power converter (“DPC”) capable of generating multi-phase power supply is disclosed. DPC, in one embodiment, includes a first switching bridge, second switching bridge, patch component, first phase generator, and second phase generator. The first switching bridge is coupled to a DC bus and configured to extract a first portion of the DC bus in accordance with a first phase of DC waveform. The second switching bridge, in one aspect, extracts a second portion of the DC bus in accordance with a second phase of DC waveform. The patch component is capable of generating a first patch waveform in response to a third portion of the DC bus. The first phase generator is configured to generate a first phase AC waveform based on the first portion of the DC bus and a first patch waveform.

Abstract: A DC/AC power converter (“DPC”) capable of generating multi-phase power supply is disclosed. DPC, in one embodiment, includes a first switching bridge, second switching bridge, patch component, first phase generator, and second phase generator. The first switching bridge is coupled to a DC bus and configured to extract a first portion of the DC bus in accordance with a first phase of DC waveform. The second switching bridge, in one aspect, extracts a second portion of the DC bus in accordance with a second phase of DC waveform. The patch component is capable of generating a first patch waveform in response to a third portion of the DC bus. The first phase generator is configured to generate a first phase AC waveform based on the first portion of the DC bus and a first patch waveform.

Abstract: An integrated high and low voltage ride through test system, comprising a primary system and a secondary system; the secondary system controls the primary system to realize information interaction, and is connected to a power grid and a wind generation set via an inlet wire switch cabinet and an outlet wire switch cabinet of the primary system; the integrated high and low voltage ride through test system actually simulates voltage drop and rise characteristics in a power grid failure, ensures that when generating a low voltage and a high voltage, the change of a voltage phase angle and power quality are consistent with actual power grid failure characteristics, and enables coherent low voltage and high voltage ride through capacity testing on the wind generation set in a primary test process.

Abstract: A wireless monitoring receiver and system use multiple video data feeds from a plurality of cameras. The video feeds are transmitted using a multi-antenna technique, and decoded by a multi-antenna processor. The resulting transmissions are resistant to noise, interference, etc., and can be focused using antenna beams to achieve a simple form of location encryption.

Abstract: A system and method for maintaining timing compatibility for high rate wireless transceivers employs a cycle stealing technique so that latencies introduced by multi-antenna signal processors in an access point can be masked. A speculative pre-stored, predetermined preamble is issued in response to a data transmission initiation from another access point, so that a responsive packet is sent within an acceptable protocol timing interval.

Abstract: A wireless data processing system uses a selectively enabled multi-antenna processor to demodulate N separate data signals from M separate antennas simultaneously. The multi-antenna processor is adapted to respond to changing channel conditions between two access points, so that it selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc.

Abstract: A method of operating a wireless data processing system to selectively enable a multi-antenna processor to demodulate N separate data signals from M separate antennas simultaneously. The multi-antenna processor is adapted to respond to changing channel conditions between two access points, so that it selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc.

Abstract: A single chip integrated circuit wireless data processor demodulates N separate data signals from M separate antennas simultaneously. The multi-antenna processor can be coupled to a baseband processor on the IC, so that it responds to changing channel conditions between two access points, and selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc. to improve a performance of the baseband processor.

Abstract: A wireless monitoring receiver and system use multiple video data feeds from a plurality of cameras. The video feeds are transmitted using a multi-antenna technique, and decoded by a multi-antenna processor. The resulting transmissions are resistant to noise, interference, etc., and can be focused using antenna beams to achieve a simple form of location encryption.

Abstract: A wireless monitoring receiver and system use multiple video data feeds from a plurality of cameras. The video feeds are transmitted using a multi-antenna technique, and decoded by a a multi-antenna processor. The resulting transmissions are resistant to noise, interference, etc., and can be focused using antenna beams to achieve a simple form of location encryption.

Abstract: A modulating mechanism is provided comprising a first storage and a corresponding first DAC, and a second storage and a corresponding second DAC. The first storage stores an adjusted digital representation of a first waveform, while the second storage stores an adjusted digital representation of a second waveform. The adjusted representation of the first waveform is adjusted to compensate for the deviation effects experienced by the first DAC (e.g. amplitude deviation, DC offset, non-linearity, etc.). The adjusted representation of the second waveform is adjusted to compensate for the deviation effects experienced by the second DAC. In effect, the adjusted representations of the first and second waveforms cause the DAC's to exhibit the proper behavior, despite the presence of the deviation effects. By storing and using adjusted digital representations of waveforms in this manner, many benefits can be realized, including for example, eliminating the need for any analog compensation circuits.

Abstract: A system and method for maintaining timing compatibility for high rate wireless transceivers employs a cycle stealing technique so that latencies introduced by multi-antenna signal processors in an access point can be masked. A speculative pre-stored, predetermined preamble is issued in response to a data transmission initiation from another access point, so that a responsive packet is sent within an acceptable protocol timing interval.

Abstract: A method of operating a wireless data processing system to selectively enable a multi-antenna processor to demodulate N separate data signals from M separate antennas simultaneously. The multi-antenna processor is adapted to respond to changing channel conditions between two access points, so that it selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc.

Abstract: A wireless data processing system uses a selectively enabled multi-antenna processor to demodulate N separate data signals from M separate antennas simultaneously. The multi-antenna processor is adapted to respond to changing channel conditions between two access points, so that it selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc.

Abstract: A wireless monitoring receiver and system use multiple video data feeds from a plurality of cameras. The video feeds are transmitted using a multi-antenna technique, and decoded by a a multi-antenna processor. The resulting transmissions are resistant to noise, interference, etc., and can be focused using antenna beams to achieve a simple form of location encryption.

Abstract: A single chip integrated circuit wireless data processor demodulates N separate data signals from M separate antennas simultaneously. The multi-antenna processor can be coupled to a baseband processor on the IC, so that it responds to changing channel conditions between two access points, and selectively kicks in if there is noise, interference, frequency fading, a need for an enhanced data rate, a need for an increased operating range, etc. to improve a performance of the baseband processor.

Abstract: A modulating mechanism is provided comprising a first storage and a corresponding first DAC, and a second storage and a corresponding second DAC. The first storage stores an adjusted digital representation of a first waveform, while the second storage stores an adjusted digital representation of a second waveform. The adjusted representation of the first waveform is adjusted to compensate for the deviation effects experienced by the first DAC (e.g. amplitude deviation, DC offset, non-linearity, etc.). The adjusted representation of the second waveform is adjusted to compensate for the deviation effects experienced by the second DAC. In effect, the adjusted representations of the first and second waveforms cause the DAC's to exhibit the proper behavior, despite the presence of the deviation effects. By storing and using adjusted digital representations of waveforms in this manner, many benefits can be realized, including for example, eliminating the need for any analog compensation circuits.