Patents by Inventor Shaoning Yao
Shaoning Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10438902Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.Type: GrantFiled: September 7, 2017Date of Patent: October 8, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Vincent J. McGahay, Nicholas A. Polomoff, Shaoning Yao, Anupam Arora
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Publication number: 20190074253Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Inventors: Vincent J. MCGAHAY, Nicholas A. POLOMOFF, Shaoning YAO, Anupam ARORA
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Publication number: 20170351799Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventors: Atsushi Azuma, Yuping Cui, James A. Culp, Marco Facchini, Shaoning Yao
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Patent number: 9836570Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.Type: GrantFiled: June 6, 2016Date of Patent: December 5, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Atsushi Azuma, Yuping Cui, James A. Culp, Marco Facchini, Shaoning Yao
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Patent number: 9324634Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: GrantFiled: November 8, 2011Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Junjing Bao, Shaoning Yao, Xuesong Li, Samuel S. S. Choi
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Patent number: 9324635Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: GrantFiled: October 28, 2014Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Junjing Bao, Samuel S. S. Choi, Xuesong Li, Shaoning Yao
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Patent number: 9018097Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.Type: GrantFiled: October 10, 2012Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Hanako Henry, Tze-Man Ko, Yiheng Xu, Shaoning Yao
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Publication number: 20150041981Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Junjing Bao, Samuel S.S. Choi, Xuesong Li, Shaoning Yao
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Publication number: 20140099787Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.Type: ApplicationFiled: October 10, 2012Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas W. Dyer, Hanako Henry, Tze-Man Ko, Yiheng Xu, Shaoning Yao
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Patent number: 8623673Abstract: A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region.Type: GrantFiled: August 13, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Tze-Man Ko, Yiheng Xu, Shaoning Yao
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Publication number: 20130113102Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Shaoning Yao, Xuesong Li, Samuel S. S. Choi
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Patent number: 8237246Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.Type: GrantFiled: January 19, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Lawrence A. Clevenger, Vincent J. McGahay, Satyanarayana V. Nitta, Shaoning Yao
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Publication number: 20100200960Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.Type: ApplicationFiled: January 19, 2010Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Lawrence A. Clevenger, Vincent J. McGahay, Satyanarayana V. Nitta, Shaoning Yao