Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: The disclosure relates to a sound propagating device including a sound-reflecting component, a first baffle plate, a second baffle plate, and a baffle assembly. The sound-reflecting component has a conical surface. The first baffle plate and the second baffle plate are respectively connected to two opposite ends of the baffle assembly. The first baffle plate, the second baffle plate, and the baffle assembly are moveably located on the conical surface. An angle between the first baffle plate and the second baffle plate is changed when at least one of the first baffle plate and the second baffle plate is moved. In addition, the disclosure also relates to a loudspeaker having the sound propagating device.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET.

Abstract: A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-K dielectric layer on the substrate. Then, an oxygen-containing titanium nitride layer is formed on the high-K dielectric layer. Next, an amorphous silicon layer is formed on the oxygen-containing titanium nitride layer and followed by performing an annealing process to drive oxygen in the oxygen-containing titanium nitride layer to the high-K dielectric layer.

Abstract: A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-K dielectric layer on the substrate. Then, an oxygen-containing titanium nitride layer is formed on the high-K dielectric layer. Next, an amorphous silicon layer is formed on the oxygen-containing titanium nitride layer and followed by performing an annealing process to drive oxygen in the oxygen-containing titanium nitride layer to the high-K dielectric layer.

Abstract: A chip with electrostatic discharge protection function includes two power rails, a pin, a P-type FinFET, an N-type FinFET, two Fin-resistors, two diodes and an ESD unit. The pin is electrically connected to one power rail sequentially through one Fin-resistor and the P-type FinFET and electrically connected to the other power rail sequentially through the other Fin-resistor and the N-type FinFET. The two FinFETs are configured to have the control terminals thereof for receiving a transmission signal. The pin is further electrically connected to the two power rails through the two diodes, respectively. The ESD unit, electrically connected between the first and second power rails, is configured to provide an ESD path between the first and second power rails.

Abstract: A chip with electrostatic discharge protection function includes two power rails, a pin, a P-type FinFET, an N-type FinFET, two Fin-resistors, two diodes and an ESD unit. The pin is electrically connected to one power rail sequentially through one Fin-resistor and the P-type FinFET and electrically connected to the other power rail sequentially through the other Fin-resistor and the N-type FinFET. The two FinFETs are configured to have the control terminals thereof for receiving a transmission signal. The pin is further electrically connected to the two power rails through the two diodes, respectively. The ESD unit, electrically connected between the first and second power rails, is configured to provide an ESD path between the first and second power rails.

Abstract: A control system and a security checking method thereof is used in an embedded system. The control system includes a process module and a first memory module. The first memory module is used to store a pre-loader code and a first secure key. The security checking method includes the following steps: loading the pre-loader code and the first secure key; executing the pre-loader code to download a first program from an in-system programming module; determining whether the first program corresponds to the first secure key or not; if yes, then downloading a second program from the in-system programming module; and programming an internal program and a second secure key by the second program.

Abstract: A control system and a security checking method thereof are disclosed. The control system is used in an embedded system. The control system comprises a process module and a first memory module. The first memory module is used to store a pre-loader code and a first secure key. The security checking method comprises following steps: loading the pre-loader code and the first secure key; executing the pre-loader code to download a first program from an in-system programming module; determining whether the first program corresponds to the first secure key or not; if yes, then downloading a second program from the in-system programming module; and programming an internal program and a second secure key by the second program.