Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Abstract: Systems and methods for pulse generation in a dual voltage domain include a first and a second voltage aware branch sensitive to a low voltage domain. The first voltage aware branch includes an inverter in the low voltage domain for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain. The second voltage aware branch includes a delay element in the low voltage domain for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.

Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.

Abstract: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.

Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.