Patents by Inventor Shaori Guo
Shaori Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10970004Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.Type: GrantFiled: December 20, 2019Date of Patent: April 6, 2021Assignee: Synopsys, Inc.Inventors: Shaori Guo, Jun Cao, Jigang Yang, Subramaniam Aravindhan, Saleem Mohammad, Chandrashekar B U
-
Patent number: 10762018Abstract: Various embodiments are directed to a USB hub configured for supporting multiple data transfer speed protocols. The USB hub comprises a plurality of protocol/LINK layer components; and a physical layer component shared among the plurality of protocol/LINK layer components and supporting at least two USB connection ports. The physical layer component is in communication with each of the plurality of protocol/LINK layer components. A buffer system (including RX/TX buffers) is shared among the plurality of protocol/LINK layer components and a USB host controller component is in communication with the buffer system. The physical layer component is configured for operating in a first mode to support one of the at least two USB ports in a first operating mode; and operating in a second mode to support the at least two USB ports in a second operating mode.Type: GrantFiled: February 4, 2019Date of Patent: September 1, 2020Assignee: SYNOPSYS, INC.Inventors: Shaori Guo, Jun Cao, Fei Ren
-
Publication number: 20200201800Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Applicant: Synopsys, Inc.Inventors: Shaori GUO, Jun CAO, Jigang YANG, Subramaniam ARAVINDHAN, Saleem MOHAMMAD, Chandrashekar B U
-
Patent number: 9858205Abstract: A system includes a cache and a cache-management component. The cache includes a plurality of cache lines that correspond to a plurality of device endpoints. The cache-management component is configured to receive a transfer request block (TRB) for data transfer involving a device endpoint. In response to a determination that the cache both (i) does not include a cache line assigned to the device endpoint and (ii) does not include an empty cache line, the cache-management component assigns, to the device endpoint, a last cache line that includes a most recently received TRB in the cache, and stores the received TRB to the last cache line.Type: GrantFiled: November 4, 2016Date of Patent: January 2, 2018Assignee: MARVELL WORLD TRADE LTD.Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Qunzhao Tian, Jeanne Q. Cai, Shaori Guo
-
Publication number: 20170052904Abstract: A system includes a cache and a cache-management component. The cache includes a plurality of cache lines that correspond to a plurality of device endpoints. The cache-management component is configured to receive a transfer request block (TRB) for data transfer involving a device endpoint. In response to a determination that the cache both (i) does not include a cache line assigned to the device endpoint and (ii) does not include an empty cache line, the cache-management component assigns, to the device endpoint, a last cache line that includes a most recently received TRB in the cache, and stores the received TRB to the last cache line.Type: ApplicationFiled: November 4, 2016Publication date: February 23, 2017Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Qunzhao Tian, Jeanne Q. Cai, Shaori Guo
-
Patent number: 9489311Abstract: Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line.Type: GrantFiled: June 6, 2014Date of Patent: November 8, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Qunzhao Tian, Jeanne Q. Cai, Shaori Guo
-
Patent number: 9367511Abstract: System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit.Type: GrantFiled: July 16, 2014Date of Patent: June 14, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Jeanne Q Cai, Yan Zhang, Shaori Guo
-
Publication number: 20150026369Abstract: System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit.Type: ApplicationFiled: July 16, 2014Publication date: January 22, 2015Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Jeanne Q. Cai, Yan Zhang, Shaori Guo
-
Publication number: 20140365731Abstract: Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line.Type: ApplicationFiled: June 6, 2014Publication date: December 11, 2014Inventors: Xingzhi Wen, Yu Hong, Hefei Zhu, Qunzhao Tian, Jeanne Q. Cai, Shaori Guo
-
Patent number: 8891022Abstract: Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.Type: GrantFiled: August 9, 2010Date of Patent: November 18, 2014Assignee: Telegent Systems, Inc.Inventors: Shaori Guo, Zu Bing Yuan, Andrew J. Burstein
-
Patent number: 8797835Abstract: A first device comprising a transceiver module configured to begin transmission of a first signal to a second device. A control module is configured to, in response to the transceiver module receiving a second signal during the transmission of the first signal to the second device, determine whether the second signal corresponds to crosstalk by having the transceiver module suspend the transmission of the first signal. In response to the transceiver module continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does not correspond to crosstalk. In response to the transceiver module not continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does correspond to crosstalk.Type: GrantFiled: August 24, 2012Date of Patent: August 5, 2014Assignee: Marvell International Ltd.Inventors: Zhenyu Zhang, Dongxin Zhou, Baolei Xie, Shaori Guo, Jeanne Q. Cai, Eric Hung
-
Publication number: 20120320966Abstract: A method and circuitry for decoding an encoded video data stream which corresponds to a selected channel which is one of a plurality of channels of a broadcast spectrum.Type: ApplicationFiled: February 14, 2011Publication date: December 20, 2012Applicant: Telegent Systems Inc. c/o M & C Corporate Services LimitedInventors: Shaori Guo, Zubing Yuan, Jun Ding
-
Patent number: 8301949Abstract: A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.Type: GrantFiled: September 9, 2009Date of Patent: October 30, 2012Assignee: Telegent Systems, Inc.Inventor: Shaori Guo
-
Patent number: 8115874Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.Type: GrantFiled: September 16, 2005Date of Patent: February 14, 2012Assignee: Trident Microsystems (Far East) Ltd.Inventors: Shaori Guo, Selliah Rathnam, Gwo Giun Lee
-
Publication number: 20120033139Abstract: Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.Type: ApplicationFiled: August 9, 2010Publication date: February 9, 2012Inventors: Shaori GUO, Zu Bing Yuan, Andrew J. Burstein
-
Publication number: 20110099330Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.Type: ApplicationFiled: September 16, 2005Publication date: April 28, 2011Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Shaori Guo, Selliah Rathnam, Gwo Giun Lee
-
Publication number: 20100080305Abstract: A device to output video and/or audio data (for example, corresponding to a selected channel which is one of a plurality of channels of a broadcast spectrum), the device comprising (i) baseband processor circuitry to demodulate a baseband signal into a data stream (for example, MPEG type data stream, such as an MPEG-2 transport or program data stream) having a plurality of packets including a plurality of video and/or audio packets wherein each video and/or audio packet includes video and/or audio payload, (ii) de-multiplexer circuitry, coupled to the baseband processor circuitry, to: (a) de-multiplex the data stream to obtain the video and/or audio payload of the plurality of video and/or audio packets, (b) detect and locate one or more errors in one or more of the video and/or audio packets, and (c) generate error characterization data (for example, information which is representative of the type of error and/or the location of the error in the video and/or audio payload) which is representative of or charaType: ApplicationFiled: September 23, 2009Publication date: April 1, 2010Inventors: Shaori Guo, Shi Cheng, Zhubing Yuan
-
Publication number: 20100050052Abstract: A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.Type: ApplicationFiled: September 9, 2009Publication date: February 25, 2010Inventor: Shaori Guo
-
Patent number: 7610544Abstract: A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.Type: GrantFiled: May 18, 2006Date of Patent: October 27, 2009Assignee: Telegent Systems, Inc.Inventor: Shaori Guo
-
Publication number: 20060282749Abstract: A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.Type: ApplicationFiled: May 18, 2006Publication date: December 14, 2006Inventor: Shaori Guo