Patents by Inventor Shao-wei Yang

Shao-wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413074
    Abstract: A method for forming a semiconductor device structure is disclosed. The method includes forming one or more first conductive features in a first dielectric layer, forming a metal layer on each of the one or more first conductive features, forming a first etch stop layer over the metal layer, forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer, and forming a second conductive feature in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 12, 2024
    Inventors: Cheng-Chin Lee, Hsin-Yen Huang, Yen Ju Wu, Shao-Kuan Lee, Kuang-Wei Yang, Hsiao-Kang Chang
  • Patent number: 12164235
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Hua Wang, Kueilin Ho, Cheng Wei Sun, Zong-You Yang, Chih-Chun Chiang, Yi-Fam Shiu, Chueh-Chi Kuo, Heng-Hsin Liu, Li-Jui Chen
  • Patent number: 12155111
    Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Ju Yu, Shao-Lun Yang, Chun-Hung Yeh, Hong Jie Chen, Tsung-Wei Lu, Wei Shuen Kao
  • Publication number: 20240379416
    Abstract: A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Publication number: 20240379560
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Shao-Kuan LEE, Cherng-Shiaw TSAI, Cheng-Chin LEE, Hsiaokang CHANG, Kuang-Wei YANG, Hsin-Yen HUANG, Shau-Lin SHUE
  • Publication number: 20240379413
    Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Chin LEE, Cherng-Shiaw TSAI, Shao-Kuan LEE, Ting-Ya LO, Chi-Lin TENG, Hsiao-Kang CHANG, Kuang-Wei YANG, Hsin-Yen HUANG, Shau-Lin SHUE
  • Publication number: 20240371690
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Cheng-Chin LEE, Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Hsin-Yen HUANG, Hsiaokang CHANG, Shau-Lin SHUE
  • Publication number: 20240363400
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12132000
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Cherng-Shiaw Tsai, Kuang-Wei Yang, Hsin-Yen Huang, Hsiaokang Chang, Shau-Lin Shue
  • Publication number: 20240329361
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Publication number: 20240321500
    Abstract: A magnetic component includes a core, at least one coil, a first heat dissipating member and a second heat dissipating member. The core includes at least one outer leg and an inner leg. The at least one coil is wound around the inner leg. The first heat dissipating member is disposed on a first side and a top side of the core. The second heat dissipating member is disposed on a second side and the top side of the core. The first heat dissipating member and the second heat dissipating member have a first joint region, a second joint region and a third joint region on the top side. Projections of the first joint region and the second joint region do not overlap with the inner leg. A projection of at least one of the first heat dissipating member and the second heat dissipating member overlaps with the inner leg.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 26, 2024
    Applicant: CYNTEC CO., LTD.
    Inventors: Yung-Shou Hsu, Chien-Lin Chen, Shao-Wei Chang, Chun-Ying Liao, Hsieh-Shen Hsieh, Ying-Teng Chang, Chia-Hao Yang
  • Publication number: 20240321498
    Abstract: A magnetic component includes a core and at least one coil. The core includes at least one outer leg and an inner leg. The inner leg is separated from an upper inner surface of the core. The inner leg is at least partially divided into a plurality of separated portions along a length direction of the inner leg. The at least one coil is wound around the inner leg.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 26, 2024
    Applicant: CYNTEC CO., LTD.
    Inventors: Yung-Shou Hsu, Chien-Lin Chen, Shao-Wei Chang, Chun-Ying Liao, Hsieh-Shen Hsieh, Ying-Teng Chang, Chia-Hao Yang
  • Patent number: 12094764
    Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Hsiao-Kang Chang, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Hsin-Yen Huang, Shau-Lin Shue
  • Patent number: 12074060
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Shao-Kuan Lee, Kuang-Wei Yang, Cherng-Shiaw Tsai, Hsin-Yen Huang, Hsiaokang Chang, Shau-Lin Shue
  • Patent number: 12067898
    Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors: identify a student within the educational environment based on the sensor data: detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment: generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Shao-Wen Yang, Addicam V. Sanjay, Karthik Veeramani, Gabriel L Silva, Marcos P. Da Silva, Jose A. Avalos, Stephen T. Palermo, Glen J. Anderson, Meng Shi, Benjamin W. Bair, Pete A. Denman, Reese L. Bowes, Rebecca A. Chierichetti, Ankur Agrawal, Mrutunjayya Mrutunjayya, Gerald A. Rogers, Shih-Wei Roger Chien, Lenitra M. Durham, Giuseppe Raffa, Irene Liew, Edwin Verplanke
  • Patent number: 12062572
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Gary Liu, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20240184341
    Abstract: A keyboard device for an electronic device includes a keyboard main body and a protection plate member. The protection plate member is pivotally coupled to the keyboard main body. Consequently, the keyboard main body is covered by the protection plate member, or a first angle is formed between the protection plate member and the keyboard main body. The protection plate member includes a first plate and a second plate. The keyboard main body is pivotally coupled to a first end of the first plate. The second plate is pivotally coupled to a second end of the first plate. After the protection plate member is rotated relative to the keyboard main body and the first angle is formed between the protection plate member and the keyboard main body, the protection plate member is further adjusted to a selected usage mode.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 6, 2024
    Inventors: Shao-Wei Yang, Chin-Lung Chan, Yi-Hsien Lin
  • Publication number: 20240172850
    Abstract: A protective cover assembly is provided, which includes a bracket and a biaxial structure. The bracket has a first portion and a second portion pivotally connected to each other. The biaxial structure has a first rotating shaft and a second rotating shaft, in which a portion of the first portion of the bracket away from the second portion is configured to be pivotally connected to or separated from the first rotating shaft or magnetically connected to or separated from the first rotating shaft, and the second rotating shaft is configured to be pivotally connected to a component.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 30, 2024
    Inventors: Shao-Wei Yang, Yi-Hsien Lin
  • Publication number: 20240045072
    Abstract: A laser detection system includes a light source module, an optical isolator, a scanner, and a detector. The light source module is configured for emitting a first laser having a first polarization direction. The optical isolator is on an optical path of the first laser configured to emit a second laser by transmitting the first laser from the light source module and prevent the second laser from transmitting toward the light source module. The scanner is on an optical path of the second laser and configured for reflecting the second laser to project a reference light to the target to be tested. The detector is configured to receive detection light reflected by the target to be tested and obtain position information of the target to be tested according to the detection light.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 8, 2024
    Inventors: KUO-FONG TSENG, SHAO-WEI YANG
  • Patent number: 10672570
    Abstract: A keyswitch structure includes a base plate, a keycap, a first support, and a second support. The keycap is located above the base plate. The first support is connected to and between the keycap and the base plate and has an upper connection portion, a lower connection portion, and a protruding limitation portion. The upper connection portion is located between the lower connection portion and the protruding limitation portion. The first support is rotatably connected to the keycap and the base plate through the upper connection portion and the lower connection portion respectively. The protruding limitation portion is located close to and under the cap body. The second support is connected to and between the keycap and the base plate. The keycap moves up and down relative to the base plate through the first support and the second support.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 2, 2020
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chih-Hao Chen, Po-Wei Tsai, Chun-Yuan Wang, Kuan-Te Lin, Shao-Wei Yang, Ling-Hsi Chao