Abstract: Various sockets for multiple sizes of chip package substrates are disclosed. In one aspect, an apparatus is provided that includes a socket that has a peripheral wall defining an interior space adapted to receive either of a first semiconductor chip package substrate and a second semiconductor chip package substrate. The first semiconductor chip package substrate has a first size and a first plurality of structural features and the second semiconductor chip package substrate has a second size different than the first size and a second plurality of structural features. The socket has a third plurality of structural features operable to engage the structural features of either of semiconductor chip package substrates to selectively enable the first semiconductor chip package substrate to be located at a first preselected position in the interior space and the second semiconductor chip package substrate to be located at a second preselected position in the interior space.

Abstract: Various sockets for multiple sizes of chip package substrates are disclosed. In one aspect, an apparatus is provided that includes a socket that has a peripheral wall defining an interior space adapted to receive either of a first semiconductor chip package substrate and a second semiconductor chip package substrate. The first semiconductor chip package substrate has a first size and a first plurality of structural features and the second semiconductor chip package substrate has a second size different than the first size and a second plurality of structural features. The socket has a third plurality of structural features operable to engage the structural features of either of semiconductor chip package substrates to selectively enable the first semiconductor chip package substrate to be located at a first preselected position in the interior space and the second semiconductor chip package substrate to be located at a second preselected position in the interior space.

Abstract: A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.

Abstract: A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.

Abstract: A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.