Patents by Inventor Sharad Murari
Sharad Murari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10088884Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.Type: GrantFiled: October 23, 2015Date of Patent: October 2, 2018Assignee: NXP B.V.Inventors: Kenneth Jaramillo, Madan Mohan Reddy Vemula, Sharad Murari, Abhijeet Chandrakant Kulkarni, Krishnan Tiruchi Natarajan
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Patent number: 9667253Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.Type: GrantFiled: April 2, 2015Date of Patent: May 30, 2017Assignee: NXP B.V.Inventors: Dominicus Marinus Roozeboom, Sharad Murari, Harold Garth Hanson
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Publication number: 20170115711Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.Type: ApplicationFiled: October 23, 2015Publication date: April 27, 2017Inventors: Kenneth Jaramillo, Madan Mohan Reddy Vemula, Sharad Murari, Abhijeet Chandrakant Kulkarni, Krishnan Tiruchi Natarajan
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Publication number: 20150214948Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventors: Dominicus Marinus Roozeboom, Sharad Murari, Harold Garth Hanson
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Patent number: 9000808Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.Type: GrantFiled: May 28, 2010Date of Patent: April 7, 2015Assignee: NXP B.V.Inventors: Dominicus M. Roozeboom, Sharad Murari, Harold Garth Hanson
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Patent number: 8674726Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.Type: GrantFiled: May 11, 2012Date of Patent: March 18, 2014Assignee: NXP B.V.Inventor: Sharad Murari
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Patent number: 8463962Abstract: According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.Type: GrantFiled: August 1, 2007Date of Patent: June 11, 2013Assignee: NXP B.V.Inventor: Sharad Murari
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Publication number: 20130127512Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.Type: ApplicationFiled: May 11, 2012Publication date: May 23, 2013Inventor: Sharad Murari
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Publication number: 20110291704Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Inventors: Dominicus M. Roozeboom, Sharad Murari, Harold Garth Hanson
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Publication number: 20100315134Abstract: Multi-lane PCI express busses devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used for synchronizing data transfers between IC dies of a plurality of integrated-circuits (IC) dies. In a first IC die, a synchronizing signal is received and latched in a first clock domain and in the first IC die to produce a first latched output signal. The latched output signal is provided for use by each of the plurality of IC dies. In each of the plurality of IC dies, the first latched output signal is latched in the first clock domain to produce a second latched output signal. The second latched output signal is latched in a second clock domain to produce a third latched output signal. The third latched output signal is used to synchronize a respective communication lane.Type: ApplicationFiled: March 2, 2009Publication date: December 16, 2010Applicant: NXP B.V.Inventor: Sharad Murari
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Publication number: 20100284451Abstract: According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.Type: ApplicationFiled: August 1, 2007Publication date: November 11, 2010Applicant: NXP, B.V.Inventor: Sharad Murari