Abstract: To reduce the number of memory access cycles required to process each data element in a data networking device having one or more queues and a corresponding set of data link structures, the queue and data link structures are implemented on separate memories. Each queue is maintained using separate receive and transmit queue structures. Similarly, the data memory linked list is separated into a data queue link and a data stack link. Each of these four memories comprises its own address and data bus, and all four memories may be accessed simultaneously by a controller. In a general case, processing a complete data transmission event (i.e., a data element arrival and a data element departure) may be performed with a latency of at most three steps. In the first step, the transmit queue is read to obtain the old head pointer.