Abstract: A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal having a second frequency lower than the first frequency. A voltage detection circuit is coupled to receive a supply voltage and configured to detect a droop in the supply voltage and generate a clock control signal in response to detecting a droop in the supply voltage. A selection circuit is coupled to the voltage detection circuit to receive the clock control signal and is configured to select one of the first clock signal and the second clock signal based on the clock control signal.

Abstract: A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

Abstract: A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.