Patents by Inventor Sharath Raghava

Sharath Raghava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210182187
    Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
    Type: Application
    Filed: December 24, 2020
    Publication date: June 17, 2021
    Inventors: Sharath Raghava, Nagabhushan Chitlur, Harsha Gupta
  • Publication number: 20210013887
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 10790827
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 10649927
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20190131975
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20190108145
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Applicant: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20190050361
    Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 14, 2019
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20180018118
    Abstract: In one embodiment, a method for power management includes receiving one or more state signals, each of the one or more state signals indicating whether a respective sub-block of a memory controller is idle or active, and determining whether to place the memory controller in an idle state or an active state based on the one or more state signals. The method also includes eating pulses of an input clock signal to produce a reduced-frequency clock signal if a determination is made to place the memory controller in the idle state, wherein the reduced-frequency clock signal is output to the memory controller. The method further includes passing the input clock signal to the memory controller if a determination is made to place the memory controller in the active state.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Inventors: Sharath Raghava, Jhy-ping Shaw, Vinodh Cuppu, Paul Min
  • Patent number: 9824772
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: November 21, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Patent number: 9607714
    Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 28, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Patent number: 9378169
    Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Ambuj Kumar, Brian Keith Langendorf, Sharath Raghava, Tony Yuhsiang Cheng
  • Patent number: 9368169
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140189180
    Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ambuj Kumar, Brian Keith Langendorf, Sharath Raghava, Tony Yuhsiang Cheng
  • Publication number: 20140181451
    Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Application
    Filed: December 27, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140181392
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140181391
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140181452
    Abstract: A method of training command signals for a memory module. The method includes programming a memory controller into a mode wherein a column access strobe is active for a single clock cycle. The method then programs a programmable delay line of the column access strobe with a delay value and performs initialization of the memory module. A read command is then sent to the memory module. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.
    Type: Application
    Filed: December 27, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Patent number: 7143304
    Abstract: An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: November 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Sharath Raghava, Kevin Normoyle, Christopher Furman
  • Publication number: 20040243876
    Abstract: An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Sharath Raghava, Kevin Normoyle, Christopher Furman