Abstract: The present invention is directed to a method of reducing false readings in a hypoglycemic detector that includes establishing a predetermined hypoglycemic threshold, a predetermined critical threshold, a predetermined rate of change in glucose concentration where the predetermined critical threshold is below the predetermined hypoglycemic threshold. A first sampling rate is then calculated based upon said predetermined hypoglycemic threshold, said predetermined critical threshold, and said predetermined rate of change in glucose concentration.

Abstract: The present invention is directed to a method of reducing false readings in a hypoglycemic detector that includes establishing a predetermined hypoglycemic threshold, a predetermined critical threshold, a predetermined rate of change in glucose concentration where the predetermined critical threshold is below the predetermined hypoglycemic threshold. A first sampling rate is then calculated based upon said predetermined hypoglycemic threshold, said predetermined critical threshold, and said predetermined rate of change in glucose concentration.

Abstract: A time domain technique for implementing an adaptive wall filter improves imaging of low-velocity blood flow by removing signals associated with slowly moving tissue. Adaptive wall filtering is performed by estimating wall velocity and bandwidth, and then filtering the basebanded data with a complex time domain notch filter. The wall velocity estimate determines the center frequency of a wall signal while the wall variance estimate determines the wall signal bandwidth. The complex filter coefficients selected are those which will center the complex notch filter on the wall center frequency, and which will set the filter cutoff frequencies (measured from this center frequency) to match the wall signal bandwidth.

Abstract: An ultrasonic imaging system for displaying color flow images includes a receiver which demodulates ultrasonic echo signals received by a transducer array and dynamically focuses the baseband echo signals. A color flow processor includes a time domain adaptive wall filter which automatically adjusts to changes in frequency and bandwidth of the wall signal components in the focused baseband echo signals. The mean frequency of the resulting filtered baseband echo signals is used to indicate velocity of flowing reflectors and to control color in the displayed image.

Abstract: A beam former in a PASS ultrasonic imaging system includes a set of sigma-delta modulators which operate to separately digitize the received echo signal from each transducer element. The oversampled one-bit digital representations of each echo signal are delayed as required for beam steering and focusing, and are summed together. A decimator filter reduces the sample rate of the digitized receive beam prior to display of the image resulting from the receive beam.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format.

Abstract: Arbitrary interior surfaces of a three-dimensional body are displayed from a regular array of values of at least one physical property in the interior of the body. The physical property measurements may be made with systems such as computerized tomographic x-ray, or magnetic resonance imaging. Highly parallel circuits and a highly parallel architecture permit generation of surface views in real time, i.e., sufficiently fast to support ongoing procedures such as surgical operations. These parallel circuits, realizable on large scale integrated circuit chips, perform surface normal calculations, linear interpolations and signal comparisons in simultaneously operating circuit paths which are asynchronously enabled when input data appear.

Abstract: The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.

Abstract: Instantaneous trip capability is provided to an electronic circuit breaker, which is of the type that generates trip signals by accumulating squares of power line current samples and thresholds the accumulation results. Samples of power line current are taken directly from the current transformer and analog-to-digital converter cascade generating them. The analog-to-digital converter is of an oversampling type, using a delta-sigma modulator. The samples are threshold detected against a prescribed threshold value without previous squaring, integration and detection. The threshold detector result is checked for two consecutive overcurrent indications before an instantaneous trip signal is generated.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.

Abstract: An approach to A/D converter architecture is based on a "pipelined and submerged" architecture which includes a pipeline of elemental stages (10.sub.i). Each stage of the pipeline comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16). To minimize converter nonlinearity due to component mismatches, a self calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip delta-sigma A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.

Abstract: A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

Abstract: An ultrasonic imaging processing system includes transducers and means to generate in an analog fashion, in-phase and quadrature phase signals. These signals are converted to digital form and a butterfly phase rotator circuit is employed to correct for phase differences in beam steering and focusing. In particular, speed and simplicity is achieved through the utilization of read only memory means providing appropriate function values for phase correction in conjunction with digital multiplication and summing circuitry.

Abstract: An oversampled delta-sigma analog to digital converter is used in conjuction with bias resistive means and a single bit digital to analog converter in a feedback loop to permit the utilization of the converter in a system in which the converter elements are supplied with power from the same source which supplies the analog input signal to the converter. Accordingly, a minimum number of on-chip circuit components are provided to extend the operational utility of delta-sigma converter/modulation devices and particularly to permit their utilization in electronic circuit breaker chips and devices.

Abstract: A pair of feedback accumulators are employed in conjunction with an oversampled analog to digital converter to generate the squared binary representation of the analog input signal. Advantage is taken of the particular form of the output waveform from oversampled analog to digital converter circuits to generate not only a standard digital output, but also the squared output after a plurality of bit-time periods L. The circuit avoids the utilization of digital multiplier circuits to perform the squaring function. The circuit is particularly applicable in the construction of electronic circuit breakers which must compute a binary representation of the square of an analog input current level signal, I.sup.2.

Abstract: Sampled and digitized in-phase and quadrature phase signals are algebraically accumulated in offset accumulators, the contents of which are periodically employed to adjust the value of offset correction factors added to each signal path. Additionally, the absolute values of the in-phase and quadrature phase signals are accumulated in gain accumulators, the contents of which are periodically employed to adjust the gain factor multiplier in one of the signal paths.

Abstract: A simple digital filter having only a single multiplier operates to extract the pilot tone from a demodulated and digitized FM stereo signal. The number of poles in the filter is chosen so that the filter output is also usable to produce a digitized representation of the carrier tone for the left minus right stereo channel. This signal is in turn used to decode the input representation into the desired left and right channel signals. The circuit of the present invention is particularly amenable to fabrication on an integrated circuit chip.

Abstract: A frequency modulated signal is converted into a pair of baseband signals by mixing the signal with a pair of phase-quadrature reference signals of substantially carrier center frequency. The double reference frequency component of each of the baseband signals is filtered to obtain I and Q signals. The I and Q signals constitute in rectangular coordinates the components of a vector represented in polar coordinates by R and .theta. where R is the maximum amplitude of the I and Q signals and .theta. is the instantaneous angle represented by the arctangent of the I signal divided by the Q signal. The I and Q signals are sampled to provide a sequence of sets of signal samples. For each set of signal samples the angle .theta. is obtained. A sequence of changes in the values of the angle .theta. over successive sampling periods is obtained and represents the deviation in frequency of the FM carrier corresponding to changes in amplitude of the modulating signal.