Patents by Inventor Shardendu Shekhar
Shardendu Shekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11831341Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.Type: GrantFiled: August 24, 2020Date of Patent: November 28, 2023Assignee: Arm LimitedInventors: Shardendu Shekhar, Andy Wangkun Chen, Yew Keong Chong
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Patent number: 11586445Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: GrantFiled: November 27, 2019Date of Patent: February 21, 2023Assignee: Arm LimitedInventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Publication number: 20210157603Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Publication number: 20200389181Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Shardendu Shekhar, Andy Wangkun Chen, Yew Keong Chong
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Patent number: 10756753Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.Type: GrantFiled: October 25, 2018Date of Patent: August 25, 2020Assignee: Arm LimitedInventors: Shardendu Shekhar, Andy Wangkun Chen, Yew Keong Chong
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Patent number: 10641822Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: GrantFiled: November 20, 2017Date of Patent: May 5, 2020Assignee: ARM LimitedInventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Publication number: 20200136643Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: Shardendu Shekhar, Andy Wangkun Chen, Yew Keong Chong
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Publication number: 20180074116Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Patent number: 9823298Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: GrantFiled: August 12, 2015Date of Patent: November 21, 2017Assignee: ARM LimitedInventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Publication number: 20170045576Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan