Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Abstract: A method of fabricating an IC includes forming a layer stack thereon including silicon nitride layer on a first silicon oxide layer, with a second silicon oxide layer thereon on a substrate including a semiconductor material. The layer stack is etched to form ?1 trench that is at least 2 microns deep into the semiconductor material. A dielectric liner is formed on sidewalls and a bottom of the trench. A polysilicon layer is formed on the dielectric liner that fills the trench and extends lateral to the trench. Chemical mechanical planarization (CMP) processing stops on the silicon nitride layer to remove the polysilicon layer and the second silicon oxide layer to form a trench structure having a polysilicon fill. After the CMP processing, thermal oxidation oxidizes exposed regions of the polysilicon layer to form a polysilicon oxide layer. After the thermal oxidizing, the silicon nitride layer is removed.

Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Abstract: A method of fabricating an IC includes forming a layer stack thereon including silicon nitride layer on a first silicon oxide layer, with a second silicon oxide layer thereon on a substrate including a semiconductor material. The layer stack is etched to form ?1 trench that is at least 2 microns deep into the semiconductor material. A dielectric liner is formed on sidewalls and a bottom of the trench. A polysilicon layer is formed on the dielectric liner that fills the trench and extends lateral to the trench. Chemical mechanical planarization (CMP) processing stops on the silicon nitride layer to remove the polysilicon layer and the second silicon oxide layer to form a trench structure having a polysilicon fill. After the CMP processing, thermal oxidation oxidizes exposed regions of the polysilicon layer to form a polysilicon oxide layer. After the thermal oxidizing, the silicon nitride layer is removed.

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: A microelectronic device includes a substrate comprising a semiconductor material having a top surface. An epitaxial layer is located on the top surface of the substrate. A doped buried layer is located within the semiconductor material, and the top surface has a surface recess over the buried layer. The surface recess has a maximum step height no greater than about 5 nanometers. A method of forming the microelectronic device is also disclosed.

Abstract: A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is implanted through the screen layer exposed by an implant mask into the substrate; the implant mask blocks antimony from the substrate outside the NBL area. The implant mask is removed, leaving the screen layer, which has the same thickness over the NBL area and the area outside the NBL, on the surface. Silicon dioxide is formed during an anneal/drive process, both in the NBL area and outside the NBL area. Slightly more silicon dioxide is formed in the NBL area, consuming more silicon there and so forming a shallow silicon recess. An epitaxial layer is grown on the top surface of the substrate. A structure for the microelectronic device is also disclosed.

Abstract: A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is implanted through the screen layer exposed by an implant mask into the substrate; the implant mask blocks antimony from the substrate outside the NBL area. The implant mask is removed, leaving the screen layer, which has the same thickness over the NBL area and the area outside the NBL, on the surface. Silicon dioxide is formed during an anneal/drive process, both in the NBL area and outside the NBL area. Slightly more silicon dioxide is formed in the NBL area, consuming more silicon there and so forming a shallow silicon recess. An epitaxial layer is grown on the top surface of the substrate. A structure for the microelectronic device is also disclosed.

Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.

Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.