Patents by Inventor Sharma DEEPAK
Sharma DEEPAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10950724Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.Type: GrantFiled: March 26, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
-
Patent number: 10699052Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: GrantFiled: August 1, 2019Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
-
Publication number: 20190354655Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
-
Publication number: 20190288109Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.Type: ApplicationFiled: March 26, 2019Publication date: September 19, 2019Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
-
Patent number: 10402528Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: GrantFiled: December 11, 2015Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
-
Patent number: 10325898Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.Type: GrantFiled: June 28, 2017Date of Patent: June 18, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sharma Deepak, Rajeev Ranjan, Kuchanuri Subhash, Chulhong Park, Jaeseok Yang, Kwanyoung Chun
-
Patent number: 10297687Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.Type: GrantFiled: November 22, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
-
Publication number: 20180151728Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.Type: ApplicationFiled: November 22, 2017Publication date: May 31, 2018Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
-
Publication number: 20180130786Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.Type: ApplicationFiled: June 28, 2017Publication date: May 10, 2018Inventors: SHARMA DEEPAK, RAJEEV RANJAN, KUCHANURI SUBHASH, CHULHONG PARK, JAESEOK YANG, KWANYOUNG CHUN
-
Patent number: 9947661Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: GrantFiled: July 5, 2017Date of Patent: April 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Raheel Azmat, Sharma Deepak, Chulhong Park
-
Publication number: 20170309627Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: ApplicationFiled: July 5, 2017Publication date: October 26, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Raheel AZMAT, Sharma Deepak, Chulhong Park
-
Patent number: 9748238Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: GrantFiled: July 11, 2016Date of Patent: August 29, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Raheel Azmat, Sharma Deepak, Chulhong Park
-
Publication number: 20160322355Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: ApplicationFiled: July 11, 2016Publication date: November 3, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Raheel AZMAT, Sharma DEEPAK, Chulhong PARK
-
Patent number: 9418990Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: GrantFiled: June 11, 2015Date of Patent: August 16, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Raheel Azmat, Sharma Deepak, Chulhong Park
-
Publication number: 20160180002Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: ApplicationFiled: December 11, 2015Publication date: June 23, 2016Inventors: Chul-Hong Park, SU-HYEON KIM, SHARMA DEEPAK
-
Publication number: 20160099243Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.Type: ApplicationFiled: June 11, 2015Publication date: April 7, 2016Inventors: Raheel AZMAT, Sharma DEEPAK, Chulhong PARK