Abstract: An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.

Abstract: A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization delimiter. The processing includes comparing the candidate delimiter with a reference delimiter to identify at least one error in the candidate delimiter; and basing the determination of whether the datum indicates the synchronization delimiter at least on a bit position of of each error.

Abstract: A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization delimiter. The processing includes comparing the candidate delimiter with a reference delimiter to identify at least one error in the candidate delimiter; and basing the determination of whether the datum indicates the synchronization delimiter at least on a bit position of of each error.