Abstract: A method includes generating a model of a software program in which, at each cycle of the model, a program counter and at most one non-program-counter variable change value. The method also includes generating at least one disjunctive partition and/or at least one partial disjunctive partition for each variable of the model. The method also includes computing an image and/or a pre-image using partial disjunctive partitions. A model checker includes a modeler to generate a model of a software program in which, at each cycle of the model, a program counter and at most one non-program-counter variable change value.

Abstract: Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language.

Abstract: A method for verifying software program code includes specifying a property that the software program code is expected to satisfy. The software program code and the property are transformed into an initial logical formula in a static single assignment (SSA) form, the formula including variables. A loop in the software program code is identified. Successive over-approximations are applied to a portion of the initial logical formula corresponding to the loop in order to produce a modified logical formula in the SSA form that represents a finite over-approximation of a set of states that are reachable by the loop. It is verified that the software program code satisfies the specified property by determining whether there is an assignment of the variables that satisfies the modified logical formula.

Abstract: A computer-implemented method for verifying a target system includes defining a specification including properties applicable to the target system. Execution sequences of the target system are identified. A set of the execution sequences is grouped into an equivalence class characterized by a common control flow. A symbolic representation of the equivalence class is evaluated so as to verify a compliance of the set of the execution sequences with one or more of the properties.

Abstract: A model checker includes a model checker to generate a model of a piece of generally asynchronous hardware in which the set of variables includes a separate process chooser variable and the remainder of the variables are divided into disjoint sets of groups. At each cycle of the model, the process chooser and maximally, variables from one group of variables change values.

Abstract: A method includes generating a model of a software program in which, at each cycle of the model, a program counter and at most one non-program-counter variable change value. The method also includes generating at least one disjunctive partition and/or at least one partial disjunctive partition for each variable of the model. The method also includes computing an image and/or a pre-image using partial disjunctive partitions. A model checker includes a modeler to generate a model of a software program in which, at each cycle of the model, a program counter and at most one non-program-counter variable change value.