Abstract: Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.

Abstract: A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whether that particular cache line is in use, and is used to arbitrate among various requesters for the same cache line. When at least two requests for the same cache line is received, a cache arbiter examines the status bit to determine if the requested cache line is in use. If the cache line is not already in use, the cache arbiter selects, and sends a signal granting the request to, the requesters one at a time to allow access to the contested cache line, while allowing concurrent access to the cache memory to other requesters requesting different cache lines. The semaphore mechanism allows exchanges of signals between the cache arbiter and the requesters to provide an orderly arbitration of multiple requests for the same cache line.

Abstract: A method, apparatus, and system for processing a plurality of outstanding data requests from an expansion device connected to a computer system. The processing of one data request may commence before a previous request has been fully processed. Multiple data requests may be fetched from the computer system and fulfilled in an overlapping fashion. Data from a subsequent data request may be fetched prior to completion of the data return for a previous request. A record of each outstanding data request and returned requested data is stored. The returned requested data is returned to the expansion device in the order in which the requested data was requested.

Abstract: Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events.

Abstract: A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.

Abstract: Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events.

Abstract: A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an “owner” or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory.

Abstract: A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a cache tag unit. A read lock is set when a request is made to obtain the requested data when it is not resident in a local cache. When the cache line containing the requested data is snooped out and the read lock is set, then the cache line is set in a snapshot state. The snapshot state assures that only the original I/O device receives the read data when it has been altered subsequent to the time the original DMA read request was made. Once the data is returned to the original I/O device, the cache line is invalidated in order to prevent another I/O device from reading the stale data. Prefetched data is marked as such and cannot be marked as snapshot data.

Abstract: A device for arbitrating access to a resource by a plurality of agents includes logic configured to associate requesting ones of the agents with access tokens. The number of the access tokens assigned to each requesting agent is proportional to its bandwidth or speed in comparison with the other requesting agents. A is selector configured to sequence through the access tokens and select respective ones of the requesting agents associated with the access tokens. The logic may dynamically reconfigure token allocation and distribution to only those agents having a pending service request or may skip tokens allocated to agents not having a pending request. The distribution of tokens is preferably uniform over the total bandwidth space of the agents or requesting agents. In one implementation tokens are in the form of binary numbers.

Abstract: A cache status data structure in a cache memory system provides a large amount of status data, which various requesters, e.g., processors and I/O devices, may read, modify and/or write to, in order to allows flexibility in the manner in which the various requesters access the cache memory. The cache status data structure is implemented as a cache structure block having a plurality of cache status bits for each cache line of the cache memory. The cache status block comprises one or more read port and one or more write port, from which, upon presenting the line entry number of the cache line of interest, a requester may read and/or write back modified status bits. The cache status bits in the cache data structure includes include a significant amount of information, including, e.g.