Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

Abstract: A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.

Abstract: A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.

Abstract: A system and method for reduced scan pin logic scanning is provided. The system may include a reduced test pin integrated circuit having at least one scan chain comprising a plurality of sequentially connected flip-flop circuits. Digital logic circuitry (also referred to as random logic) is connected to at least one of the plurality of flip-flop circuits in the at least one scan chain. Combined test data pins, with separate clock and scan enable pins are contemplated, as well as additional internal circuitry for the integrated circuit that can eliminate a separate scan enable pin, or both the separate scan enable and clock pins. Circuitry for permitting simultaneous test data input and output on the same pin is also contemplated.

Abstract: An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.

Abstract: An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.

Abstract: An apparatus includes a signal processing circuit and at least two oscillators that provide, respectively, at least first and second reference signals. The apparatus further comprise a selection circuit. The selection circuit provides to the signal processing circuit one of the first and second reference signals depending on a mode of operation of the signal processing circuit.

Abstract: An apparatus includes a signal processing circuit and at least two oscillators that provide, respectively, at least first and second reference signals. The apparatus further comprise a selection circuit. The selection circuit provides to the signal processing circuit one of the first and second reference signals depending on a mode of operation of the signal processing circuit.

Abstract: In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.

Abstract: In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.