Patents by Inventor Sharon Shi

Sharon Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546750
    Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: January 28, 2020
    Assignee: Vishay-Siliconix
    Inventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
  • Patent number: 10084037
    Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 25, 2018
    Assignee: VISHAY-SILICONIX
    Inventors: Qufei Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9893168
    Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 13, 2018
    Assignee: VISHAY-SILICONIX
    Inventors: Yang Gao, Kuo-In Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9887266
    Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: February 6, 2018
    Assignee: Vishay-Siliconix
    Inventors: The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen
  • Publication number: 20170117354
    Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 27, 2017
    Inventors: Qufei Chen, Kyle Terrill, Sharon Shi
  • Publication number: 20160359018
    Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Yang Gao, Kuo-In Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9484451
    Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: November 1, 2016
    Assignee: VISHAY-SILICONIX
    Inventors: Qufei Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9443974
    Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: September 13, 2016
    Assignee: Vishay-Siliconix
    Inventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
  • Patent number: 9431530
    Abstract: A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: August 30, 2016
    Assignee: Vishay-Siliconix
    Inventors: Robert Q. Xu, Kuo-In Chen, Karl Lichtenberger, Sharon Shi, Qufei Chen, Kyle Terrill
  • Patent number: 9425306
    Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: August 23, 2016
    Assignee: Vishay-Siliconix
    Inventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
  • Patent number: 9419129
    Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: August 16, 2016
    Assignee: Vishay-Siliconix
    Inventors: Yang Gao, Kuo-In Chen, Kyle Terrill, Sharon Shi
  • Publication number: 20160225622
    Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
    Type: Application
    Filed: January 5, 2016
    Publication date: August 4, 2016
    Applicant: Vishay-Siliconix
    Inventors: Hamilton LU, The-Tu CHAU, Kyle TERRILL, Deva N. PATTANAYAK, Sharon SHI, Kuo-In CHEN, Robert XU
  • Patent number: 9230810
    Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 5, 2016
    Assignee: Vishay-Siliconix
    Inventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
  • Patent number: 8883580
    Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Vishay-Siliconix
    Inventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
  • Publication number: 20140235023
    Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.
    Type: Application
    Filed: December 27, 2012
    Publication date: August 21, 2014
    Applicant: VISHAY-SILICONIX
    Inventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
  • Patent number: 8409954
    Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 2, 2013
    Assignee: Vishay-Silconix
    Inventors: The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen
  • Patent number: 8368126
    Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: February 5, 2013
    Assignee: Vishay-Siliconix
    Inventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-In Chen
  • Publication number: 20120220092
    Abstract: Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 30, 2012
    Applicant: VISHAY-SILICONIX
    Inventors: Madhur Bobde, Qufei Chen, Misbah Ul Azam, Kyle Terrill, Yang Gao, Sharon Shi
  • Publication number: 20120211828
    Abstract: In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: VISHAY-SILICONIX
    Inventors: Madhur Bobde, Qufei Chen, Misbah Ul Azam, Kyle Terrill, Yang Gao, Sharon Shi
  • Publication number: 20110089486
    Abstract: A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.
    Type: Application
    Filed: May 26, 2010
    Publication date: April 21, 2011
    Applicant: VISHAY-SILICONIX
    Inventors: Robert Q. Xu, Kuo-In Chen, Karl Lichtenberger, Sharon Shi, Qufei Chen, Kyle Terrill