Abstract: A method, system and apparatus for controlling the duty cycle of a clock to optimize duty cycle correction and non over-lapping clock generation. The first system generates a reference voltage and one or more clock signals. A comparison is made between the DC level of an output clock and the reference voltage. A correct duty cycle of the clock signal is equal to a predetermined ratio of high time to low time, within an acceptable margin, wherein the ratio of high time to low time is derived from a first resistor and a second resistor. A second system is developed to generate non-overlap clock signals with non-overlap gap control, wherein a reference voltage of a first circuit network is the reference voltage of a second circuit network; thereby generating a single reference signal for the non-overlap circuit network.