Patents by Inventor Sharyu Vijay Mukhekar

Sharyu Vijay Mukhekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736594
    Abstract: A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 22, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Dhaval Shah, Sunil Puranik, Manoj Nambiar, Mahesh Damodar Barve, Ishtiyaque Shaikh, Piyush Manavar, Sharyu Vijay Mukhekar
  • Publication number: 20220311839
    Abstract: A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.
    Type: Application
    Filed: June 16, 2021
    Publication date: September 29, 2022
    Applicant: Tata Consultancy Services Limited
    Inventors: Dhaval SHAH, Sunil PURANIK, Manoj NAMBIAR, Mahesh Damodar Barve, Ishtiyaque Shaikh, Piyush Manavar, Sharyu Vijay Mukhekar