Patents by Inventor Shashank C. Merchant

Shashank C. Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200029108
    Abstract: A computing system identifies multiple matching points between (i) query fingerprints representing a media stream being received by a client and (ii) reference fingerprints, each identified matching point defining a respective match between a query fingerprint timestamped with client time defined according to a clock of the client and a reference fingerprint timestamped with true time defined according to a timeline within a known media stream. Further, the computing system performs linear regression based on the timestamps of the matching points, to establish a mapping between true time and client time. The computing system then uses the mapping to determine a client-time point at which the client should perform a content revision or other action with respect to the media stream being received by the client. And the computing system causes the client to perform the content revision or other action at the determined client-time point.
    Type: Application
    Filed: October 22, 2018
    Publication date: January 23, 2020
    Inventors: Peter Dunker, Markus K. Cremer, Shashank C. Merchant, Kurt R. Thielen
  • Publication number: 20200021877
    Abstract: A computing system identifies a media stream being received by a client, based on fingerprint matching conducted with query fingerprints generated by the client at a frame rate. The computing system then causes the client to increase the frame rate, in order to facilitate establishment by the computing system of synchronous lock between true time within the media stream and client time according to an clock of the client. The computing system then uses the established synchronous lock as a basis to map a true-time point at which a content revision should be performed in the media stream to a client-time point at which the client should perform the content revision. And the computing system causes the client to perform the content revision at the determined client-time point.
    Type: Application
    Filed: October 22, 2018
    Publication date: January 16, 2020
    Inventors: Kurt R. Thielen, Shashank C. Merchant, Peter Dunker, Markus K. Cremer, Steven D. Scherf
  • Patent number: 10506275
    Abstract: A computing system identifies a media stream being received by a client, based on fingerprint matching conducted with query fingerprints generated by the client at a frame rate. The computing system then causes the client to increase the frame rate, in order to facilitate establishment by the computing system of synchronous lock between true time within the media stream and client time according to an clock of the client. The computing system then uses the established synchronous lock as a basis to map a true-time point at which a content revision should be performed in the media stream to a client-time point at which the client should perform the content revision. And the computing system causes the client to perform the content revision at the determined client-time point.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: December 10, 2019
    Assignee: Gracenote, Inc.
    Inventors: Kurt R. Thielen, Shashank C. Merchant, Peter Dunker, Markus K. Cremer, Steven D. Scherf
  • Publication number: 20180359040
    Abstract: A computing system obtains a fingerprint of video content being rendered by a video presentation device, including a first portion representing a pre-established video segment and a second portion representing a dynamically-defined video segment. While obtaining the query fingerprint, the computing system (a) detects a match between the first portion of the query fingerprint and a reference fingerprint that represents the pre-established video segment, (b) based on the detecting of the match, identifies the video content being rendered, (c) after identifying the video content being rendered, applies a trained neural network to at least the second portion of the query fingerprint, and (d) detects, based on the applying of the neural network, that rendering of the identified video content continues. And responsive to at least the detecting that rendering of the identified video content continues, the computing system then takes associated action.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 13, 2018
    Inventors: Dewey Ho Lee, Shashank C. Merchant, Markus K. Cremer
  • Publication number: 20180359041
    Abstract: A computing system obtains a fingerprint of video content being rendered by a video presentation device, including a first portion representing a pre-established video segment and a second portion representing a dynamically-defined video segment. While obtaining the query fingerprint, the computing system (a) detects a match between the first portion of the query fingerprint and a reference fingerprint that represents the pre-established video segment, (b) based on the detecting of the match, identifies the video content being rendered, (c) after identifying the video content being rendered, applies a trained neural network to at least the second portion of the query fingerprint, and (d) detects, based on the applying of the neural network, that rendering of the identified video content continues. And responsive to at least the detecting that rendering of the identified video content continues, the computing system then takes associated action.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 13, 2018
    Inventors: Dewey Ho Lee, Shashank C. Merchant, Markus K. Cremer
  • Patent number: 6778547
    Abstract: An integrated multiport switch operating in a packet switched network utilizes an internal rules checker (IRC) to process data frames. The IRC employs a modular, pipelined architecture that enables data frames to be processed simultaneously, thereby increasing data throughput.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: August 17, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Shashank C. Merchant
  • Patent number: 6636523
    Abstract: A novel method of flow control in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in a plurality of data queues to be processed by the decision making engine. The data queues allocated to the receive ports are monitored to produce a flow control threshold signal for a selected data queue to indicate a heavy traffic condition of a receive port corresponding to the selected data queue. For example, the flow control threshold signal may indicate that the receive port is close to an overflow condition. Monitoring of a selected data queue may be performed by comparing a write pointer indicating a memory location for writing the data blocks into the selected data queue with a read pointer indicating a memory location for reading the data blocks from the selected data queue.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: October 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Vengchong Lau, Shashank C. Merchant
  • Patent number: 6546010
    Abstract: Network switch modules are cascaded in a prescribed sequence to support higher port requirements. The network switch modules may circulate a received frame indefinitely if the frame is not destined for any one of the output ports of the cascaded arrangement of network switch modules. Frame forwarding logic within each of the cascaded network switch modules is employed to determine when a network switch module should cease forwarding the received frame. Specifically, the frame forwarding logic takes the frame out of circulation based upon the sequence identifier of the network switch module and an embedded identifier associated with the frame.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: April 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shashank C. Merchant, Ching Yu, Robert Alan Williams
  • Patent number: 6463032
    Abstract: A novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a prescribed algorithm. Then, a forwarding decision is made to determine the transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state. For example, pointers indicating memory locations for storing the corresponding received data packets may be transferred via the overflow bypass when the overflow state is detected.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: October 8, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Vengchong Lau, Shashank C. Merchant, John M. Chiang
  • Patent number: 6460088
    Abstract: An integrated multiport switch operating in a packet switched network provides the capability to alter VLAN tags on a port by port basis. An internal rules checker (IRC) employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The IRC further generates a port vector, and thereby, outputs a forwarding descriptor that instructs Port Vector FIFO logic (PVF) on how to process the data frame.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Shashank C. Merchant
  • Patent number: 6330248
    Abstract: A gigabit network node having a media access controller outputting data frames at gigabit rates uses multiple 100 MB/s media interface links coupled to a physical interface to enable implementation of a gigabit network using low cost data links. A modified reconciliation layer, also referred to as a media interface, receives a data frame from a gigabit MAC and selectively stores the received packet data into one of a plurality of transmit buffers associated with the respective 100 MB/s media interface links, according to a path selection arbitration logic in the media interface. The path selection arbitration logic may operate according to an equal priority scheme, where each received data frame is routed according to a round-robin scheme.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: December 11, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gopal S. Krishna, Mohan V. Kalkunte, Shashank C. Merchant
  • Patent number: 6222825
    Abstract: Apparatus and method for more precise controlling of congestion on a network, provides for remote controlling of a remote station on the network by a local station to configure the remote station into a remote loopback configuration. With the remote station thus configured, the local station is then able to determine the link latency of the link, during auto-negotiation, for example. Provided with the link latency, a congestion control algorithm in the local station may be adjusted to account for the link latency to better control the input data streams by controlling when the congestion relieving control signal, such as a PAUSE frame, is transmitted to the remote station to inhibit transmission and relieve congestion.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Mangin, Jayant Kadambi, Mohan Kalkunte, Shashank C. Merchant
  • Patent number: 6112294
    Abstract: An arrangement in a processor circuit for concurrently executing a plurality of instructions. An instruction control unit concurrently supplies a plurality of instruction addresses to an instruction memory. Each clock cycle, the instruction memory receives one instruction address from the instruction control unit based on a count value and selectively fetches and outputs corresponding to the received instruction address. An instruction decoder decodes, each clock cycle, the instruction output from the instruction memory the preceding clock cycle while identifying a memory address and an instruction operation for each fetched instruction. A memory interface, based on the count value, selectively supplies to an external memory, each clock cycle, one of the supplied memory addresses and identified by the instruction decoder for the respective fetched instructions.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: August 29, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shashank C. Merchant, Thomas Jefferson Runaldue
  • Patent number: 6094439
    Abstract: A Gigabit network node having a media access controller outputting packet data at Gigabit rates uses multiple 100 MB/s physical layer links coupled to a physical interface having a data router to enable implementation of a Gigabit network using low cost data links. A modified reconciliation layer, also referred to as a multi-Media Independent Interface (m-MII) selectively transmits at least a portion of the packet data from the MAC onto the plurality of physical layer links. The physical m-MII interface may output separate packet data on separate physical layer links to increase the effective data transmission rate, may output the same packet data on multiple transmission paths to improve quality of service by establishing redundant data links, or any combination thereof. Priority channels may also be provided on selected physical layer links to provide quality of service and cost of service options within an Ethernet work group environment.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: July 25, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gopal S. Krishna, Mohan V. Kalkunte, Shashank C. Merchant
  • Patent number: 6081523
    Abstract: A Gigabit network node having a media access controller outputting packet data at Gigabit rates uses multiple 100 MB/s media interface links coupled to a physical interface to enable implementation of a Gigabit network using low cost data links. A modified reconciliation layer, also referred to as a media interface, receives a data packet from a Gigabit MAC and divides the received data packet into multiple data segments having a prescribed length. The multiple segments are output on the multiple media interface links according to a prescribed output protocol, enabling a corresponding media interface at the destination station to recompile the data packet from the received segments from the multiple transmission paths. The transmission of the segments upon multiple transmission paths provides an efficient load balancing of data traffic among the multiple transmission paths.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: June 27, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shashank C. Merchant, Mohan V. Kalkunte, Gopal Krishna
  • Patent number: 5995488
    Abstract: Interpacket delay times are modified in full-duplex Ethernet network devices by calculating for each network station a delay interval based on a time to transmit a data packet at the network rate and a calculated time to transmit the data packet at a desired transmission rate. The network station waits the calculated delay time following a packet transmission before transmitting the next data packet, ensuring that the overall output transmission rate of the network station corresponds to the assigned desired transmission rate. The desired transmission rate is received as a media access control (MAC) control frame from a network management entity, such as a switched hub. Hence, each network station operates at the desired transmission rate, minimizing the occurrence of congestion and eliminating the necessity of PAUSE frames.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: November 30, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan Kalkunte, Shashank C. Merchant, Jayant Kadambi
  • Patent number: 5933413
    Abstract: A network interface stores data frames between a host computer and a network in a buffer memory. The network interface stores data frames received from the host computer via a peripheral component interconnect (PCI) bus in a transmit buffer for transmission on the network. The network interface also stores data from the network in a receive buffer for transfer to a host computer memory via the PCI bus. A priority control selectively allocates host computer resources based on network transmission and network reception by the network interface, and based on available space in the receive buffer, available data in the transmit buffer, and the estimated length of data packets received from the network. The selective allocation of host computer resources minimizes transmit buffer underflow and receive buffer overflow.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: August 3, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shashank C. Merchant, Jeffrey Roy Dwork