Abstract: A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.

Abstract: Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.

Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

Abstract: Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: Described embodiments provide for dynamically controlling a scheduling rate of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. The traffic manager maintains one or more scheduling data structures for each node in the scheduling hierarchy. If the traffic manager receives a rate reduction request corresponding to a given node of the scheduling hierarchy, the traffic manager updates one or more indicators in the scheduling data structure corresponding to the given node and removes the given node from the scheduling hierarchy, thereby reducing the scheduling rate of the node.