Patents by Inventor Shashidhar Shreeshail SHINTRI

Shashidhar Shreeshail SHINTRI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions
    Patent number: 9735057
    Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shashidhar Shreeshail Shintri, Min-hwa Chi
  • FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS
    Publication number: 20150311120
    Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 29, 2015
    Inventors: Shashidhar Shreeshail SHINTRI, Min-hwa CHI