Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: A system, apparatus, method and article to reduce power consumption are described. The method may include receiving a power management request for a reduced power consumption state from each of a plurality of processors. A power management request for the reduced power consumption state may be sent to a controller to cache data. Each of the plurality of processors may be instructed to enter the reduced power consumption state. An interrupt may be received to return to an active power consumption state. A power management request may be sent to the controller to flush cached data into a memory. Each of the plurality of processors may be instructed to enter the active power consumption state. Other embodiments are described and claimed.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.