Patents by Inventor Shaun Joseph Cunningham

Shaun Joseph Cunningham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6960490
    Abstract: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: November 1, 2005
    Assignee: EpiTactix Pty Ltd.
    Inventor: Shaun Joseph Cunningham
  • Patent number: 6919261
    Abstract: A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate 210 and multiple semiconductor tiles 220 bonded to the surface of the metallic substrate 210. The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 19, 2005
    Assignee: Epitactix PTY LTD
    Inventor: Shaun Joseph Cunningham
  • Publication number: 20040124501
    Abstract: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.
    Type: Application
    Filed: August 4, 2003
    Publication date: July 1, 2004
    Applicant: CSIRO Telecommunications and Industrial Physics
    Inventor: Shaun Joseph Cunningham
  • Publication number: 20040007763
    Abstract: A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate 210 and multiple semiconductor tiles 220 bonded to the surface of the metallic substrate 210. The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.
    Type: Application
    Filed: March 13, 2003
    Publication date: January 15, 2004
    Applicant: Commonwealth Scientific and Industrial Research Organization Campbell, Australia
    Inventor: Shaun Joseph Cunningham