Patents by Inventor Shaun P. Whalen

Shaun P. Whalen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7831979
    Abstract: A processor comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is operative to retrieve from the memory circuitry an interrupt polling instruction which causes selection of an active enabled interrupt and generation of an interrupt vector for the selected active enabled interrupt. In conjunction with the selection and generation operations, an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread at an appropriate time subsequent to interruption of that thread.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: November 9, 2010
    Assignee: Agere Systems Inc.
    Inventor: Shaun P. Whalen
  • Patent number: 7675913
    Abstract: A packet, cell or other data segment received in a physical layer device from a link layer device via an interface bus is processed to determine a port address for the data segment in the physical layer device. The port address, which may be an MPHY address, is determined using a combination of a first address value obtained from a link layer address portion of the data segment and a second address value obtained from a payload portion of the data segment. The data segment is stored in a memory location identified by the port address. The memory location may comprise a particular queue of the physical layer device.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: March 9, 2010
    Assignee: Agere Systems Inc.
    Inventors: Algernon P. Henry, Shaun P. Whalen, Harold J. Wilson
  • Publication number: 20080123657
    Abstract: A packet, cell or other data segment received in a physical layer device from a link layer device via an interface bus is processed to determine a port address for the data segment in the physical layer device. The port address, which may be an MPHY address, is determined using a combination of a first address value obtained from a link layer address portion of the data segment and a second address value obtained from a payload portion of the data segment. The data segment is stored in a memory location identified by the port address. The memory location may comprise a particular queue of the physical layer device.
    Type: Application
    Filed: August 24, 2006
    Publication date: May 29, 2008
    Inventors: Algernon P. Henry, Shaun P. Whalen, Harold J. Wilson
  • Patent number: 7080113
    Abstract: A virtually parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: July 18, 2006
    Assignee: Agere Systems Inc.
    Inventors: Hyun Lee, Shaun P. Whalen
  • Patent number: 6622153
    Abstract: A virtual parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a resource/time-sharing methodology with multiple sequential computational stages.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: September 16, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Hyun Lee, Shaun P. Whalen
  • Patent number: 6269440
    Abstract: An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is programmed with readable assembly language and requires neither vector registers nor a lot of extra registers to implement.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: July 31, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: John S. Fernando, Frank T. Lemmon, Shaun P. Whalen
  • Patent number: 6052766
    Abstract: A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: April 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Michael R. Betker, John S. Fernando, Frank Lemmon, Shaun P. Whalen
  • Patent number: 5935266
    Abstract: A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: August 10, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Stefan Thurnhofer, Shaun P. Whalen