Abstract: Technologies for remote direct memory access (RDMA) congestion control include a requester device and a responder device in communication over an Ethernet network. The requester device sends routable RDMA packets to the responder device over the Ethernet network. The packets may be RDMA over Converged Ethernet version 2 (RoCEv2) packets. The responder device determines whether any of the received packets have been marked by the network with a congestion encountered codepoint. If so, the responder device sends an acknowledgment packet with an express congestion notification bit set in the RDMA base transport header. The requester device updates a congestion window as a function of a number of congested packets acknowledged and a total number of packets acknowledged. Those operations may be performed by a network controller of each of the requester device and the responder device. Other embodiments are described and claimed.

Abstract: Technologies for remote direct memory access (RDMA) congestion control include a requester device and a responder device in communication over an Ethernet network. The requester device sends routable RDMA packets to the responder device over the Ethernet network. The packets may be RDMA over Converged Ethernet version 2 (RoCEv2) packets. The responder device determines whether any of the received packets have been marked by the network with a congestion encountered codepoint. If so, the responder device sends an acknowledgment packet with an express congestion notification bit set in the RDMA base transport header. The requester device updates a congestion window as a function of a number of congested packets acknowledged and a total number of packets acknowledged. Those operations may be performed by a network controller of each of the requester device and the responder device. Other embodiments are described and claimed.

Abstract: A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus.