Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: A flash memory cell comprises a substrate having a trench formed below the substrate surface, a vertical bit line or auxiliary gate deposited in the trench below the surface, a drain region formed in the substrate below the bit line, and a split floating gate deposited in the trench below the surface to a depth less than the vertical bit line. The floating gate includes a first vertical portion on one side of the bit line and a second vertical portion on another side of the bit line opposite the first vertical portion, with each portion of the gate being accessed by the bit line. The memory cell further includes a source region formed below the surface spaced apart from and adjacent each of the floating gate portions and a word line or control gate extending over the substrate, bit line and floating gate portions.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: An integrated circuit decoupling capacitor is divided into a plurality of discrete segments. The segments are connected electrically in parallel and are redundant to an extent that if one segment (or if desired more than one segment) fails, the remaining segments have sufficient capacitance to provide the required decoupling function. Each decoupling capacitor segment has a fuse connected in series with it. The fuse opens in response to a fault in a decoupling capacitor segment that would otherwise cause that segment to short the power supply to ground.

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid.

Abstract: An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.