Patents by Inventor Shawn Adams

Shawn Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110238273
    Abstract: The present disclosure relates to methods of detecting misalignment in a transmission synchronizer and methods of alignment. Detection of misalignment is accomplished via monitoring a performance characteristic of a power source configured to provide an engagement force to the synchronizer. Where misalignment is detected a predetermined torque is applied to the input or output side of the synchronizer to rotationally align synchronizer components.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Inventors: Shawn Adam Holland, Jeffrey James Tumavitch, Steve Craig Meisner, Bradley Dean Riedle
  • Publication number: 20110005967
    Abstract: A front opening semiconductor wafer container for large diameter wafers includes a container portion and a door. The container portion includes a left closed side, a right closed side, a closed back, an open front, and an open interior including a plurality of slots for receiving and containing the wafers. The door is attachable to the container portion to close the open front and selectively latchable to the container portion. The container portion includes a means for accommodating large diameter wafers, particularly 450 mm wafers. Optimized sag control is provided as well as enhanced structural rigidity, and wafer seating features.
    Type: Application
    Filed: January 13, 2009
    Publication date: January 13, 2011
    Applicant: ENTEGRIS, INC.
    Inventors: Barry Gregerson, Michael Shawn Adams, Jason Todd Steffens
  • Patent number: 7283471
    Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: October 16, 2007
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Maria C. Gutierrez, Shawn Adam Clayton, David R. Follett, Harold E. Roman, Nitin D. Godiwala, Richard F. Prohaska, James B. Williams
  • Publication number: 20070012732
    Abstract: Wearable Drinking Garment is a series of inner skeletal tubes lined together and attached to form an X that straps flat around the chest, back and under arm area, with sipping tube at top end and airflow stub tube at bottom end; covered and protected by inner insulated lining to lock in temperature of water/liquid in extreme weather conditions; outer mesh lining for heavy resistance against rough and extreme activities. These three together form the X-shape Vest that locks onto the body, can go under or over clothing, is hands free and lightweight with water flowing through a series of flat tubes, giving an evenly balanced comfortable glove-tight fit to the body, with easy slip on/off convenience. Compete at higher levels while never stopping to get a drink. Second generation has oxygen tubes, mini tank for better breathing, ie: medical purposes, diving, space travel, short/long term mining and more.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 18, 2007
    Inventor: Shawn Adams
  • Patent number: 7107382
    Abstract: A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: September 12, 2006
    Assignee: Emulex Design & Manufacturing Corporation
    Inventor: Shawn Adam Clayton
  • Patent number: 6931497
    Abstract: A method includes receiving a first buffer allocation command from a first processor, the allocation command including a register address associated with a pool of buffers in a shared memory, determining whether a buffer is available in the buffer pool based upon a buffer index corresponding to a free buffer, and if a buffer is determined available allocating the buffer to the first processor.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: August 16, 2005
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Shawn Adam Clayton, Shaun Andrew McMaster, Thomas V. Spencer
  • Patent number: 6874054
    Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 29, 2005
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Shawn Adam Clayton, Brian Mark Fortin, Daniel Brian Willie, John Leland Wood
  • Publication number: 20040199700
    Abstract: A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventor: Shawn Adam Clayton
  • Publication number: 20040139284
    Abstract: A method includes receiving a first buffer allocation command from a first processor, the allocation command including a register address associated with a pool of buffers in a shared memory, determining whether a buffer is available in the buffer pool based upon a buffer index corresponding to a free buffer, and if a buffer is determined available allocating the buffer to the first processor.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 15, 2004
    Inventors: Shawn Adam Clayton, Shaun Andrew McMaster, Thomas V. Spencer
  • Publication number: 20040123013
    Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Shawn Adam Clayton, Brian Mark Fortin, Daniel Brian Willie, John Leland Wood