Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.