Patents by Inventor Shawn Clayton
Shawn Clayton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160094425Abstract: Systems and methods are disclosed for configuring telematics behavior. The system includes a machine. The machine includes at least one communication module for communication to and from the machine over a network. The machine also includes a memory. The machine further includes a processor configured to receive a telematics behavior configuration file associated with a subscription number, the telematics behavior configuration file comprising at least a file transfer rule for communication over the network. The processor is also configured to store the telematics behavior configuration file in the memory. The processor is further configured to determine whether the network is available and, in response to a determination that the network is available, transfer and receive data over the network according to the telematics behavior configuration file.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Applicant: CATERPILLAR INC.Inventors: Robert Franklin SCHULZ, Shawn Clayton SARVER, Caleb Mark JORDEN, John David PARKER, Jason Robert WHITE
-
Patent number: 7295557Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: GrantFiled: May 7, 2004Date of Patent: November 13, 2007Assignee: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
-
Publication number: 20050165980Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.Type: ApplicationFiled: March 23, 2005Publication date: July 28, 2005Applicant: Emulex Design & Manufacturing CorporationInventors: Shawn Clayton, Brian Fortin, Daniel Willie, John Wood
-
Publication number: 20050066045Abstract: An integrated network interface device that supports data exchange in two or more high-speed network data transfer protocols that are based on different standards of network data transfer architectures, wherein an incoming data stream formatted in accordance with a particular network data transfer standard is processed into data not subject to the network data transfer standard to be output for further processing by a host. In one aspect, a network interface device is provided with a set of shared or common protocol independent physical link components that are used to identify the operating protocol of the incoming data, and a set of dynamically or statically re-configurable, shared or common protocol independent data transfer processing components that support data exchange via the physical link components for all the supported protocols, which may include a protocol specific link interface for each supported protocol.Type: ApplicationFiled: September 3, 2003Publication date: March 24, 2005Inventors: Neil Johnson, Kiwon Chang, Shawn Clayton
-
Publication number: 20040208181Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Applicant: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
-
Patent number: 6795442Abstract: A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.Type: GrantFiled: April 23, 1998Date of Patent: September 21, 2004Assignee: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
-
Patent number: 6791948Abstract: A network includes devices such as computers and the like, interconnected by switching nodes. The devices are identified by globally-unique identifiers, such as Ethernet MAC addresses or the like. At least some of the devices are configured to determine the topology of the network. In determining the network topology, a device operates in a series of iterations, in each iteration transmitting a request message over a path to determine whether an additional entity is present in the network. If an additional entity is present at the end of the path defined in the request message, the entity will generate a response, which is provided to the device. The device, on receiving the response, will add information concerning the entity to a network topology database, which it maintains to define the topology of the database. At least some of the devices, as they discover additional switching nodes in the network, will attempt to configure the switching nodes.Type: GrantFiled: December 27, 1999Date of Patent: September 14, 2004Assignee: Emulex CorporationInventors: Peter J. Desnoyers, Shawn A. Clayton, Nitin D. Godiwala
-
Publication number: 20030174647Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: ApplicationFiled: March 11, 2003Publication date: September 18, 2003Applicant: Emulex Corporation, a California corporationInventors: Maria C. Gutierrez, Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Richard F. Prohaska, Harold E. Roman, James B. Williams
-
Patent number: 6570850Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: GrantFiled: April 23, 1998Date of Patent: May 27, 2003Assignee: Giganet, Inc.Inventors: Maria C. Gutierrez, Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Richard F. Prohaska, Harold E. Roman, James B. Williams
-
Patent number: 5838899Abstract: A fault-isolating digital data processing apparatus includes plural functional units that are interconnected for point-to-point communications by a plurality of buses. The functional units monitor the buses to which they are attached and signal the other units in the event there are bus communication errors. The functional units can simultaneously enter into an error isolation phase, e.g., in response to a bus error signaled by one of the units. During this phase, each unit transmits test data (e.g., predetermined patterns of O's and 1's) onto at least one of its attached buses. The functional units continue to monitor the buses and to signal bus errors while the test data is being transmitted. In addition to signaling bus errors, the functional units can signal unit-level (or "board") faults when they detect fault in their own operation.Type: GrantFiled: June 5, 1996Date of Patent: November 17, 1998Assignee: Stratus ComputerInventors: William I. Leavitt, Conrad R. Clemson, Jeffrey S. Somers, John M. Chaves, David R. Barbera, Shawn A. Clayton