Abstract: A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor.

Abstract: A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor. Inside the computer system, data containing the commands written to a particular memory location in a video buffer card is applied to various signal lines located in the monitor interface cable. These signal lines are coupled to the microcontroller located in the display monitor which receives the commands and performs various controlling functions in response. Status information in the form of a command is transmitted back across a second signal line to the computer system where various software programs including drivers receive and process the status information. Display data is simultaneously transmitted over other signal lines also located in the monitor interface cable.

Abstract: A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus and the FD bus and uses the floating point processors as buffer chips.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A test mode read back function for verifying the functions of the memory display interface and a VRAM frame buffer coupled to the memory display interface, wherein the memory display interface implements programmable pixel rates and pixel depths, and programmable pixel processing functions.

Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions.