Abstract: A cake cutter includes a handle having an L-shaped blade extending therefrom. The blade includes a first section axially extending from an end of the handle and a second section perpendicularly extending from a distal end of the first section. Integrally molded with a central portion of each blade section is a raised ridge that is positioned a predetermined distance from either end of the blade section. Accordingly, the user can cut a precisely sized slice of cake or casserole by aligning the ridges with an outer edge of a cake.

Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.

Abstract: Methods for low temperature cleaning of a semiconductor surface prior to in-situ deposition have high throughput and consume very little of the thermal budget. GeH4 deposits Ge on the surface and converts any surface oxygen to GeOx. An etchant, such as Cl2 or HCl removes Ge and any GeOx and epitaxial deposition follows. A spike in Ge concentration can be left on the substrate from diffusion into the substrate. All three steps can be conducted sequentially in-situ at temperatures lower than conventional bake steps.

Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.

Abstract: Methods for low temperature cleaning of a semiconductor surface prior to in-situ deposition have high throughput and consume very little of the thermal budget. GeH4 deposits Ge on the surface and converts any surface oxygen to GeOx. An etchant, such as Cl2 or HCl removes Ge and any GeOx and epitaxial deposition follows. A spike in Ge concentration can be left on the substrate from diffusion into the substrate. All three steps can be conducted sequentially in-situ at temperatures lower than conventional bake steps.

Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.

Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.

Abstract: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.

Abstract: A multiple, independent top gated field effect transistor having an improved electron injection and reduced gate induced barrier lowering effects, and a method that allows for the destruction of metallic carbon nanotubes positioned between the source and drain of a top multi-gate transistor are provided. The field effect transistor comprises at least one carbon nanotube (14) coupled between the first and second electrodes (16, 18) and a first gate material (24) formed over a portion of the at least one carbon nanotube (14) and spaced apart from the first and second electrodes (16, 18). A dielectric material (32) is conformally coated on the first and second electrodes (16, 18), the at least one carbon nanotube (14), and the first gate material (24). A second gate material (36) is conformally coated on the dielectric material (32).

Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

Abstract: A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.

Abstract: A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.