Abstract: An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.

Abstract: An intra-chassis device multi-management domain system includes a chassis housing a host processing system connected to first device(s), a secondary processing system connected to second device(s), and a management system connected to the first and second device(s). The management system may receive a first request for management access including first management domain access credentials, determine that the first management domain access credentials allow first access to a host domain associated with the host processing system and, in response, provide the first access to the first device(s) connected to the host processing system.

Abstract: An SCP data mirroring system includes a chassis housing a central processing system and an SCP subsystem. The SCP subsystem includes an SCP memory system with different priority storage queues each storing a copy of data provided by the central processing system, along with an SCP communication system and an SCP data storage subsystem. During a first time period, the SCP data storage subsystem retrieves a first copy of the data from a first storage queue in the SCP memory system and transmits it via the SCP communication system and through a network for storage on first storage device(s). During a subsequent second time period, the SCP data storage system retrieves a second copy of the data from a lower priority second storage queue in the SCP memory system and transmits it via the SCP communication system and through the network for storage on second storage device(s).

Abstract: A secondary processor device ownership system includes a chassis that houses a plurality of devices, a secondary processing system, and a central processing system that includes an integrated switch device that is coupled to each of the plurality of devices and the secondary processing system. The central processing system is configured to provide a device ownership subsystem that configures the central processing system to own a first subset of the plurality of devices, configures the secondary processing system to own a second subset of the plurality of devices, and hides the second subset of the plurality of devices from at least one application provided by the central processing system.

Abstract: An SCP power unavailability data storage system includes a chassis housing a power system, a central processing system, and an SCP subsystem that are coupled together. The SCP subsystem includes a volatile SCP memory system storing data provided by the central processing system, an SCP processing system coupled to the volatile SCP memory system, and an SCP communication system that, when power is unavailable from the power system, utilizes power received via its data/power port(s) and provides that power to the volatile SCP memory system and the SCP processing system. An SCP data storage engine provided by the SCP processing system will, in response to an unavailability of power from the power system, operate using power received via the data/power port(s), retrieve data stored in the volatile SCP memory system, and transmit the data via port(s) on the SCP communication system and through a network for storage on storage device(s).

Abstract: An SCP data mirroring system includes a chassis housing a central processing system and an SCP subsystem. The SCP subsystem includes an SCP memory system with different priority storage queues each storing a copy of data provided by the central processing system, along with an SCP communication system and an SCP data storage subsystem. During a first time period, the SCP data storage subsystem retrieves a first copy of the data from a first storage queue in the SCP memory system and transmits it via the SCP communication system and through a network for storage on first storage device(s). During a subsequent second time period, the SCP data storage system retrieves a second copy of the data from a lower priority second storage queue in the SCP memory system and transmits it via the SCP communication system and through the network for storage on second storage device(s).

Abstract: A secondary processor device ownership system includes a chassis that houses a plurality of devices, a secondary processing system, and a central processing system that includes an integrated switch device that is coupled to each of the plurality of devices and the secondary processing system. The central processing system is configured to provide a device ownership subsystem that configures the central processing system to own a first subset of the plurality of devices, configures the secondary processing system to own a second subset of the plurality of devices, and hides the second subset of the plurality of devices from at least one application provided by the central processing system.

Abstract: An SCP power unavailability data storage system includes a chassis housing a power system, a central processing system, and an SCP subsystem that are coupled together. The SCP subsystem includes a volatile SCP memory system storing data provided by the central processing system, an SCP processing system coupled to the volatile SCP memory system, and an SCP communication system that, when power is unavailable from the power system, utilizes power received via its data/power port(s) and provides that power to the volatile SCP memory system and the SCP processing system. An SCP data storage engine provided by the SCP processing system will, in response to an unavailability of power from the power system, operate using power received via the data/power port(s), retrieve data stored in the volatile SCP memory system, and transmit the data via port(s) on the SCP communication system and through a network for storage on storage device(s).

Abstract: An intra-chassis device multi-management domain system includes a chassis housing a host processing system connected to first device(s), a secondary processing system connected to second device(s), and a management system connected to the first and second device(s). The management system may receive a first request for management access including first management domain access credentials, determine that the first management domain access credentials allow first access to a host domain associated with the host processing system and, in response, provide the first access to the first device(s) connected to the host processing system.

Abstract: A secondary processor proxied device ownership system includes a chassis housing a plurality of devices, a secondary processing system, and a central processing system that includes an integrated switch device that is coupled to each of the plurality of devices and the secondary processing system. The central processing system enter a Basic Input/Output System (BIOS) mode in which the central processing system provides a BIOS that is configured to execute instructions and, using the BIOS, receives a transaction that was generated by the secondary processing system and that is directed to a first device that is include in the plurality of devices, and executes the transaction on the first device.

Abstract: A secondary processor device ownership assignment system includes a chassis that houses devices, a secondary processing system, a central processing system that includes an integrated switch device that is coupled to each of the devices and the secondary processing system, and a device ownership subsystem that is coupled to the central processing system. The device ownership system accesses device information for a subset of the devices that will be owned by the secondary processing system, and configures the device information for the subset of the devices such that the subset of the devices are hidden from an operating system provided by the central processing system. The secondary processing system reconfigures the device information for the subset of the plurality of devices such that the subset of the plurality of devices are accessible by the secondary processing system.

Abstract: A build on-demand chassis with a universal bay system that can be assembled into different configurations to support different system requirements from end users includes positionable partitions and a bay support assembly for each set of devices. A controller communicates with a microcontroller unit (MCU) in each bay support assembly to determine a slot identifier and a type of device supported by the bay support assembly to provide greater flexibility in what configurations are possible. When a processor in the information handling system sends an instruction for a type of device, the controller knows the location and capabilities of the device and manages the communication.

Abstract: An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.

Abstract: An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.

Abstract: A fail-safe power limit (FSPL) can be applied to components that lose communication with a management module (MM) to determine a safe power level at which to operate. The FSPL may be computed by the management module (MM) for the information handling system and distributed to components in the information handling system. By computing a FSPL and transmitting the FSPL to the components, a larger amount of the available power can be used by the components. This allows the components to continue operating at performance levels closer to or equivalent to levels available when the management module (MM) is operating normally. The FSPL may be updated at set times and/or on a periodic schedule such that the FSPL used by the components when communication is lost with the management module (MM) reflects a recent operating state of the components.

Abstract: An equipment rack that includes a modular compute chassis, a modular processing unit located in the modular compute chassis and where the modular processing unit is configured to remove from the front of the modular compute chassis in a frontward direction, relative to the front side of the modular compute chassis, and an air mover unit located in the modular processing unit and where the air mover unit is configured to remove from a rear side of the modular processing unit in a rearward direction, relative to the front side of modular compute chassis.

Abstract: Apparatuses for direct cabled connections of fabric signals—i.e., high-speed data signals exchanged between computer processors and peripheral devices. Specifically, varying apparatus configurations are outlined herein for minimizing, if not eliminating, the routing of these fabric signals through printed circuit boards, which tend to cause signal quality degradation due to phenomena such as the skin effect and dielectric loss.

Abstract: A fail-safe power limit (FSPL) can be applied to components that lose communication with a management module (MM) to determine a safe power level at which to operate. The FSPL may be computed by the management module (MM) for the information handling system and distributed to components in the information handling system. By computing a FSPL and transmitting the FSPL to the components, a larger amount of the available power can be used by the components. This allows the components to continue operating at performance levels closer to or equivalent to levels available when the management module (MM) is operating normally. The FSPL may be updated at set times and/or on a periodic schedule such that the FSPL used by the components when communication is lost with the management module (MM) reflects a recent operating state of the components.

Abstract: An information handling system may include a field-programmable gate array (FPGA), and a hypervisor to manage virtual machines. The hypervisor may host a first FPGA service manager that loads instances of binary images for FPGA services into respective regions of the FPGA for the benefit of software applications. The virtual machine may host a second FPGA service manager that receives a request for an FPGA service from a software application running in the virtual machine, and sends a query to the first FPGA service manager to determine whether a binary image for the FPGA service exists on the FPGA. The first FPGA service manager may receive the query and, if a binary image instance for the FPGA service exists on the FPGA, may provide information to the second FPGA service manager to facilitate the use of the FPGA service by the software application running in the virtual machine.

Abstract: An information handling system may include a field-programmable gate array (FPGA) and an FPGA service manager, within a hypervisor, to receive from software running in a virtual machine a request for an FPGA service, load a bitstream for the service into a first region of the FPGA, increment a count of concurrent users of the bitstream, determine, subsequent to a further update to the count, whether the count is zero or non-zero, and reclaim the first region of the FPGA if the count is zero. The bitstream may be received from the virtual machine or from a catalog of bitstreams maintained on the hypervisor. The FPGA service manager may load a second instance of the bitstream into a second region of the FPGA dependent on execution constraints specified in a bitstream header, or may load a bitstream for a second service into the second region of the FPGA.