Patents by Inventor Shawn M. Luke

Shawn M. Luke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8823491
    Abstract: Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shawn M. Luke, Michael R. Ouellette, Karl V. Swanke, Sebastian T. Ventrone
  • Patent number: 8595468
    Abstract: A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shawn M. Luke, John Sargis, Jr., Daneyand J. Singley
  • Publication number: 20130181838
    Abstract: Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: International Business Machines Corporation
    Inventors: Shawn M. Luke, Michael R. Ouellette, Karl V. Swanke, Sebastian T. Ventrone
  • Publication number: 20110153987
    Abstract: A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shawn M. Luke, John Sargis, JR., Daneyand J. Singley