Patents by Inventor Shawn M. O'Connor

Shawn M. O'Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030148554
    Abstract: A packaged semiconductor device (20) has a first integrated circuit die (28) having a top surface with active electrical circuitry implemented thereon. The first die (28) is mounted in a cavity (21) of a first heat spreader (22). A second die (36) having electrical circuitry implemented on a top surface is attached to the top surface of the first die (28). Both of the die (28 and 36) are electrically connected to a substrate (24) mounted on the first heat spreader (22). A second heat spreader (40) is mounted on the top surface of the second die (36). The second heat spreader (40) provides an additional path for thermal dissipation of heat generated by the second die (36).
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Mark A. Gerber, Shawn M. O'Connor, Trent A. Thompson
  • Publication number: 20030111946
    Abstract: A method of fabricating a field emission device cathode using electrophoretic deposition of carbon nanotubes in which a separate step of depositing a binder material onto a substrate, is performed prior to carbon nanotube particle deposition. First, a binder layer is deposited on a substrate from a solution containing a binder material. The substrate having the binder material deposited thereon is then transferred into a carbon nanotube suspension bath allowing for coating of the carbon nanotube particles onto the substrate. Thermal processing of the coating transforms the binder layer properties which provides for the adhesion of the carbon nanotube particles to the binder material.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventors: Albert Alec Talin, Kenneth Andrew Dean, Shawn M. O'Rourke, Bernard F. Coll, Matthew Stainer, Ravichandran Subrahmanyan
  • Publication number: 20030085463
    Abstract: A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12. 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 8, 2003
    Inventors: Mark A. Gerber, Shawn M. O'Connor, Trent A. Thompson
  • Publication number: 20020175400
    Abstract: A semiconductor device and its method of formation are disclosed wherein a first semiconductor substrate (20) and a second semiconductor substrate (21) are encapsulated in a no lead package (100). In some embodiments, a plurality of off die bond pads (30) is coupled to at least one of the first and second semiconductor substrates (20, 21). In some embodiments, the first semiconductor substrate (20) has a backside (40) which remains exposed after encapsulation.
    Type: Application
    Filed: May 26, 2001
    Publication date: November 28, 2002
    Inventors: Mark A. Gerber, Shawn M. O'Connor, Trent A. Thompson
  • Publication number: 20020163292
    Abstract: A viewing screen (100) for a display device (115) includes a glass substrate (110) having a thermal coefficient of expansion within a range of 3.5×10−6−4.5×10−6° C.−1. Viewing screen (100) further includes a black matrix (111), which is affixed to glass substrate (110), and which includes a black surround, a ductile metal, and lead titanate.
    Type: Application
    Filed: April 16, 2002
    Publication date: November 7, 2002
    Inventors: Shawn M. O'Rourke, Nick R. Munizza, Matthew Stainer
  • Patent number: 6476506
    Abstract: A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 5, 2002
    Assignee: Motorola, Inc.
    Inventors: Shawn M. O'Connor, Mark Allen Gerber, Jean Desiree Miller
  • Publication number: 20020086300
    Abstract: Newly identified signal transduction polypeptides active in taste signal transduction, and the genes encoding said polypeptides are described. Specifically, sensory proteins referred to as REPEATER, LUNCH, and 165-015 polypeptides, are described, and genes encoding the same are described, along with methods for isolating such genes and for expressing polypeptides and analyzing signal transduction interactions. Methods for identifying novel molecules or combinations of molecules that are involved in taste signal transduction in a mammal are also described, which utilize at least one of the identified signal transduction polypeptides.
    Type: Application
    Filed: April 5, 2001
    Publication date: July 4, 2002
    Inventors: Jon Elliot Adler, Shawn M. O'Connell
  • Patent number: 6406926
    Abstract: A vacuum microelectronic device (10,40) is formed by applying a first conductor (13,14) to a substrate (11) and utilizing the first conductor (13,14) to expose a dielectric material (18) and a second conductive material (19) from a back surface of the substrate (11). A second conductor (29) and a dielectric (28) are formed from the second conductive material (19) and the dielectric material (18), respectively. This method self-aligns the dielectric (28) and the second conductor (29) with the first conductor (13,14). Electron emitters (31,33) of the vacuum microelectronic device (10,40) are formed on the first conductor (13,14).
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: June 18, 2002
    Assignee: Motorola, Inc.
    Inventors: Shawn M. O'Rourke, Ravichandran Subrahmanyan
  • Patent number: 6400072
    Abstract: A viewing screen (100) for a display device (115) includes a glass substrate (110) having a thermal coefficient of expansion within a range of 3.5×10−6−4.5×10−6 °C.−1. Viewing screen (100) further includes a black matrix (111), which is affixed to glass substrate (110), and which includes a black surround, a ductile metal, and lead titanate. A method for fabricating viewing screen (100) includes the steps of: adding to a black surround paste a ductile metal paste, adding to the black surround paste lead titanate particles, depositing the black surround paste on glass substrate (110), and heating the black surround paste and glass substrate (110) to affix the black surround paste to glass substrate (110), thereby forming black matrix (111). The ductile metal paste and lead titanate particles are added in amounts sufficient to realize an extent of cracking in black matrix (111) upon repeated heating to a temperature within a range of 450-600° C.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: June 4, 2002
    Assignee: Motorola, Inc.
    Inventors: Shawn M. O'Rourke, Nick R. Munizza, Matthew Stainer