Patents by Inventor Shawn Malhotra

Shawn Malhotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for performing optimization using don't care states
    Patent number: 8904318
    Abstract: A method for designing a system on a target device includes determining a realization set of a signal that includes one or more representations of the signal where at least one of the representation is influenced by a Don't Care Set (DCS) and all representations are equivalent. The realization set is propagated through the system with the signal. The realization set is used to perform a plurality of separate optimizations on the logic.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: December 2, 2014
    Assignee: Altera Corporation
    Inventors: Shawn Malhotra, Valavan Manohararajah
  • Method and apparatus for performing optimization using Don't Care states
    Patent number: 8661381
    Abstract: A method for designing a system on a target device includes determining a realization set of a signal that includes one or more representations of the signal where at least one of the representation is influenced by a Don't Care Set (DCS) and all representations are equivalent. The realization set is propagated through the system with the signal. The realization set is used to perform a plurality of separate optimizations on the logic.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: February 25, 2014
    Assignee: Altera Corporation
    Inventors: Shawn Malhotra, Valavan Manohararajah
  • Method and apparatus for performing automated timing closure analysis for systems implemented on target devices
    Patent number: 8504970
    Abstract: A method for generating a design for a system to be implemented on a target device includes compiling the design. Information used to make a compilation decision on the design is stored. A strategy to improve timing closure on a signal path on the design is derived using the information.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: August 6, 2013
    Assignee: Altera Corporation
    Inventors: Shawn Malhotra, Mark Ari Teper, Steven Caranci, Ketan Padalia, Mark Bourgeault
  • Hardware and software debugging
    Patent number: 8214701
    Abstract: An integrated hardware and software debugging system debugs software running on a processor and debugs hardware blocks that perform operations separate from the processor. Cycle traces are recorded for hardware block operations and the data is presented to a user through the same interface used for software debugging. Where hardware blocks are implemented in configurable circuitry (such as an FPGA) from source code, hardware debugging is linked to the source code to simulate stepping through the source code.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 3, 2012
    Assignee: Altera Corporation
    Inventors: Shawn Malhotra, Deshanand Singh
  • Method and apparatus for performing compound duplication of components on field programmable gate arrays
    Patent number: 7401314
    Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with connections to the components in placement locations.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 15, 2008
    Assignee: Altera Corporation
    Inventors: Karl Schabas, Stephen Brown, Deshanand Singh, Terry Borer, Shawn Malhotra