Patents by Inventor Shawn Michael Swilley

Shawn Michael Swilley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel memories for multidimensional data access
    Patent number: 9760770
    Abstract: The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: September 12, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kenneth Hiroshi Eguro, Ray A. Bittner, Jr., George E. Smith, Shawn Michael Swilley, Rehan Ahmed
  • Hardware-amenable connected components labeling
    Patent number: 9508003
    Abstract: The subject disclosure is directed towards performing connected components in hardware, such as an FPGA, which is facilitated by a linked list structure that does not grow. During a connected components graph labeling process, when a merge is encountered, the data structure comprising labels and associated equivalency data swaps the equivalency data of the two vertices whose different labels produced the merge condition.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: November 29, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kenneth Hiroshi Eguro, George E. Smith, Shawn Michael Swilley
  • HARDWARE-AMENABLE CONNECTED COMPONENTS LABELING
    Publication number: 20150078672
    Abstract: The subject disclosure is directed towards performing connected components in hardware, such as an FPGA, which is facilitated by a linked list structure that does not grow. During a connected components graph labeling process, when a merge is encountered, the data structure comprising labels and associated equivalency data swaps the equivalency data of the two vertices whose different labels produced the merge condition.
    Type: Application
    Filed: April 15, 2014
    Publication date: March 19, 2015
    Applicant: Microsoft Corporation
    Inventors: Kenneth Hiroshi Eguro, George E. Smith, Shawn Michael Swilley
  • Parallel Memories for Multidimensional Data Access
    Publication number: 20140310496
    Abstract: The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.
    Type: Application
    Filed: June 14, 2013
    Publication date: October 16, 2014
    Inventors: Kenneth Hiroshi Eguro, Ray A. Bittner, JR., George E. Smith, Shawn Michael Swilley, Rehan Ahmed